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 missing vias in stacked power rings 

Last post Tue, Jan 26 2010 3:23 PM by MMode. 2 replies.
Started by MMode 19 Nov 2009 05:30 AM. Topic has 2 replies and 1803 views
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  • Thu, Nov 19 2009 5:30 AM

    • MMode
    • Not Ranked
    • Joined on Sat, Jul 4 2009
    • Posts 6
    • Points 90
    missing vias in stacked power rings Reply

     Hi all,

     

    we are working in a 5 metal layer process with Encounter 5.2. In our design, we have decided to stack the power rings, i.e. the VSS ring is on metal layer 1 and the VDD ring is in the same position but on metal layer 5. However, we are confronted with the following problem during power routing: If the ring's width is greater or equal to 1001 µm (drawing dimensions), the vias from metal 3 to 4 and metal 4 to 5 are missing, so the core rows are not connected to VDD.

    However, if the ring is only 1000 µm wide (or less), this problem does not occur. Unfortunately, 1000 µm is by far not enough for our design.

    Another interesting thing is that the power stripes (on metal 2) are connected correctly even when their width is greater than 1000 µm. From this we draw the conclusion that this is not a problem related to viarule definitions in our LEF technology files.

     

    Has anybody encountered a similar problem or, even better, can provide us with an explanation of this behaviour?

    Thanks in advance!

    • Post Points: 20
  • Fri, Jan 8 2010 12:33 AM

    • BobD
    • Top 25 Contributor
    • Joined on Fri, Jul 11 2008
    • Chelmsford, MA
    • Posts 247
    • Points 9,325
    Re: missing vias in stacked power rings Reply

    I was going to do some testing on a design, but I wanted to check first- are you sure you want rings that are one thousand microns wide?  That seems massive and sure to violate technology rules that limit how wide a single wire can be without needing to be split or slotted.

    Could you confirm this is the intent?  What process node is this?

    Thanks,
    Bob

    • Post Points: 20
  • Tue, Jan 26 2010 3:23 PM

    • MMode
    • Not Ranked
    • Joined on Sat, Jul 4 2009
    • Posts 6
    • Points 90
    Re: missing vias in stacked power rings Reply

     Hi Bob,

    thanks a lot for your response. We are working in a process with shrink factor, i.e. the 1000 microns wire will actually be 70 microns wide in final dimensions. The shrink factor was specified using ui_shr_scale in the configuration file. We have thoroughly checked the LEF files as well as the design rule specification documents, there is definitely no rule violated by a wire that is 1000 microns (drawing dimensions) wide. There is also not a single warning to be found in the logs that would indicate a rule violation.

    What's more, we made power stripes with a width of more than 1000 microns (just for testing purposes), and they were correctly connected.

    However, since we were not able to find a solution to this problem in time, in the end we have indeed split the ring into to two rings, this worked well. So for us, the problem is "solved". Thank you!

    • Post Points: 5
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Started by MMode at 19 Nov 2009 05:30 AM. Topic has 2 replies.