we are working in a 5 metal layer process with Encounter 5.2. In our design, we have decided to stack the power rings, i.e. the VSS ring is on metal layer 1 and the VDD ring is in the same position but on metal layer 5. However, we are confronted with the following problem during power routing: If the ring's width is greater or equal to 1001 µm (drawing dimensions), the vias from metal 3 to 4 and metal 4 to 5 are missing, so the core rows are not connected to VDD.
However, if the ring is only 1000 µm wide (or less), this problem does not occur. Unfortunately, 1000 µm is by far not enough for our design.
Another interesting thing is that the power stripes (on metal 2) are connected correctly even when their width is greater than 1000 µm. From this we draw the conclusion that this is not a problem related to viarule definitions in our LEF technology files.
Has anybody encountered a similar problem or, even better, can provide us with an explanation of this behaviour?
Thanks in advance!