Home > Community > Forums > Logic Design > Reg .VCD file generation

Share
  • Email
  • Social Web
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Reg .VCD file generation 

Last post Fri, Nov 13 2009 4:44 AM by grasshopper. 5 replies.
Started by Music 11 Nov 2009 09:14 AM. Topic has 5 replies.
Page 1 of 1 (6 items)
Sort Posts:

  • Wed, Nov 11 2009 9:14 AM

    • Music
    • Top 200 Contributor
    • Joined on Fri, Oct 30 2009
    • Hyderabad, Andhra Pradesh
    • Posts 12
    • Points 240
    Reg .VCD file generation Reply

    Hi,

     

       I need to run power analysis . so i need  .vcd file. So can any ione say how to generate a .vcd file. I have model sim, Xilix, RC compiler , SoC Encpunter 8.1 . From these can i generate a .vcd file if so let me know the steps pla.. i have lib, lef , sdc, sdf.etc file swith me.. plz help me.. i need some steps....i asked in digital forum they requested me to post here... i.e in this forum...

    Filed under:
    • Post Points: 20

  • Wed, Nov 11 2009 11:08 AM

    • grasshopper
    • Top 50 Contributor
    • Joined on Thu, Jul 17 2008
    • Chelmsford, MA
    • Posts 63
    • Points 950
    Re: Reg .VCD file generation Reply

    Please read the following link

    http://newsgroups.derkeiler.com/Archive/Comp/comp.lang.vhdl/2008-02/msg00165.html

    Seems like a reasonable explanation and probably better than anything I can provide since I do not have access to modelsim. Once you have the vcd file you can use it across the rest of the tools you mention. It is probably best to read the vcd into RC and generate a TCF to use for the rest of the tools. TCF runs faster in the end since it only contains the toggle activity

    hope this helps,

    gh-

     
    • Post Points: 20

  • Thu, Nov 12 2009 3:11 PM

    • Music
    • Top 200 Contributor
    • Joined on Fri, Oct 30 2009
    • Hyderabad, Andhra Pradesh
    • Posts 12
    • Points 240
    Re: Reg .VCD file generation Reply

     I saw your url and it was different andi couldnt get ehat i need.. i need the whole procedure to generate a vcd file either from rtl compiler or xilinx or modelsim... please help me this issue ir related to my thesis ....

    • Post Points: 20

  • Thu, Nov 12 2009 4:24 PM

    • TAM1
    • Top 150 Contributor
    • Joined on Thu, Jul 17 2008
    • HOME, PA
    • Posts 17
    • Points 265
    Re: Reg .VCD file generation Reply

    I realize that it is frustrating when everyone tells you to look somewhere else. But I can't tell you how to create a VCD file here if you are using Modelsim to simulation your netlist. This is a Cadence user's forum. If you were using Cadence's NC-Verilog or NCVHDL, you would create a VCD file using a TCL command on the simulator's interface.

     

    database -open -vcd testpatterns.vcd
    probe -all -depth all

     

    But I wouldn't know what commands you would use in Modelsim, since it is produced by another company.
    • Post Points: 20

  • Thu, Nov 12 2009 9:40 PM

    • Music
    • Top 200 Contributor
    • Joined on Fri, Oct 30 2009
    • Hyderabad, Andhra Pradesh
    • Posts 12
    • Points 240
    Re: Reg .VCD file generation Reply
    Thanks TAM1, Basically i need to calculate the power analysis in SoC Encounter. So for it i need a vcd file. Basically i have my design.v, design_testbench.v, design.sdf, .lib files, .lef files , design.sdf files that i obtained from rtl compiler. I have Model sim, xilinx and cadence encounter with me. I dnt have NC-Verilog , So i dnt use any commands for model sim i just go with gui options. But Is there a chance for me to get vcd file with my availlable options. If soo please give me the procedure or steps to get a .vcd file. If u know cadence encounter please say me how ot get power analysis in SoC Encounter 8.1.... Awaiting for your reply, Music....
    Filed under:
    • Post Points: 20

  • Fri, Nov 13 2009 4:44 AM

    • grasshopper
    • Top 50 Contributor
    • Joined on Thu, Jul 17 2008
    • Chelmsford, MA
    • Posts 63
    • Points 950
    Re: Reg .VCD file generation Reply

    As TAM1 mentioned, your simulator is the tool responsible for generating the VCD, and in your case it is not one produced by Cadence or that I am familiar with all its switches and options. I tried forwarding a link showing how this is done using modelsim but it sounds like that link may have been missing some of the information you need based on your response. I suggest you contact your Mentor AE or Mentor forum for help on modelsim. As per the other tools, you have everything you need and all of them will simply read the VCD file generated with modelsim. The documentation has detailed information on how to do that.

    good luck,

    gh-

    • Post Points: 5
Page 1 of 1 (6 items)
Sort Posts:
Started by Music at 11 Nov 2009 09:14 AM. Topic has 5 replies.