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 Reg .VCD file generation 

Last post Mon, Jan 7 2013 11:14 PM by nannasin28. 8 replies.
Started by Music 11 Nov 2009 09:14 AM. Topic has 8 replies and 6004 views
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  • Wed, Nov 11 2009 9:14 AM

    • Music
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    Reg .VCD file generation Reply

    Hi,

     

       I need to run power analysis . so i need  .vcd file. So can any ione say how to generate a .vcd file. I have model sim, Xilix, RC compiler , SoC Encpunter 8.1 . From these can i generate a .vcd file if so let me know the steps pla.. i have lib, lef , sdc, sdf.etc file swith me.. plz help me.. i need some steps....i asked in digital forum they requested me to post here... i.e in this forum...

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  • Wed, Nov 11 2009 11:08 AM

    • grasshopper
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    Re: Reg .VCD file generation Reply

    Please read the following link

    http://newsgroups.derkeiler.com/Archive/Comp/comp.lang.vhdl/2008-02/msg00165.html

    Seems like a reasonable explanation and probably better than anything I can provide since I do not have access to modelsim. Once you have the vcd file you can use it across the rest of the tools you mention. It is probably best to read the vcd into RC and generate a TCF to use for the rest of the tools. TCF runs faster in the end since it only contains the toggle activity

    hope this helps,

    gh-

     

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  • Thu, Nov 12 2009 3:11 PM

    • Music
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    Re: Reg .VCD file generation Reply

     I saw your url and it was different andi couldnt get ehat i need.. i need the whole procedure to generate a vcd file either from rtl compiler or xilinx or modelsim... please help me this issue ir related to my thesis ....

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  • Thu, Nov 12 2009 4:24 PM

    • TAM1
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    Re: Reg .VCD file generation Reply

    I realize that it is frustrating when everyone tells you to look somewhere else. But I can't tell you how to create a VCD file here if you are using Modelsim to simulation your netlist. This is a Cadence user's forum. If you were using Cadence's NC-Verilog or NCVHDL, you would create a VCD file using a TCL command on the simulator's interface.

     

    database -open -vcd testpatterns.vcd
    probe -all -depth all

     

    But I wouldn't know what commands you would use in Modelsim, since it is produced by another company.

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  • Thu, Nov 12 2009 9:40 PM

    • Music
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    Re: Reg .VCD file generation Reply
    Thanks TAM1, Basically i need to calculate the power analysis in SoC Encounter. So for it i need a vcd file. Basically i have my design.v, design_testbench.v, design.sdf, .lib files, .lef files , design.sdf files that i obtained from rtl compiler. I have Model sim, xilinx and cadence encounter with me. I dnt have NC-Verilog , So i dnt use any commands for model sim i just go with gui options. But Is there a chance for me to get vcd file with my availlable options. If soo please give me the procedure or steps to get a .vcd file. If u know cadence encounter please say me how ot get power analysis in SoC Encounter 8.1.... Awaiting for your reply, Music....
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  • Fri, Nov 13 2009 4:44 AM

    • grasshopper
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    Re: Reg .VCD file generation Reply

    As TAM1 mentioned, your simulator is the tool responsible for generating the VCD, and in your case it is not one produced by Cadence or that I am familiar with all its switches and options. I tried forwarding a link showing how this is done using modelsim but it sounds like that link may have been missing some of the information you need based on your response. I suggest you contact your Mentor AE or Mentor forum for help on modelsim. As per the other tools, you have everything you need and all of them will simply read the VCD file generated with modelsim. The documentation has detailed information on how to do that.

    good luck,

    gh-

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  • Mon, Nov 12 2012 6:54 AM

    • geezmaneti
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    Re: Reg .VCD file generation Reply

    TAM1, i know it's been a while for this thread but i'm hoping this will make it to you. I'm using Spectre from within Cadence and want to write out a .vcd file. Is this possible? I saw your tcl commands above, but i'm not even sure where i would input these and i'm not certain that Spectre has a tcl interface.

    Thanks 

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  • Mon, Nov 12 2012 7:32 AM

    • TAM1
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    Re: Reg .VCD file generation Reply

    Yes. You simply need to create a TCL file with the commands I mentioned above.

    database -open -vcd testpatterns.vcd
    probe -all -depth all

    Now, if you were running the simulator yourself from the command line, you would use an option like "-input myfile.tcl" to tell the simulator to read and execute that script file.

    I'm afraid that I don't know how Spectre interacts with the simulator, but I imagine there is a field or option that you can set that would pass that TCL script to the simulator. You'll have to get info about that from the docs or someone else who knows Spectre.

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  • Mon, Jan 7 2013 11:14 PM

    • nannasin28
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    Re: Reg .VCD file generation Reply
    TCF runs faster in the end since it only contains the toggle activity..
    2N3055
    http://www.hqew.net
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Started by Music at 11 Nov 2009 09:14 AM. Topic has 8 replies.