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 Stacked via violations in encounter power router. 

Last post Fri, Aug 31 2012 12:02 AM by snoredpig. 6 replies.
Started by deeps 04 Nov 2009 05:36 AM. Topic has 6 replies and 2648 views
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  • Wed, Nov 4 2009 5:36 AM

    • deeps
    • Top 500 Contributor
    • Joined on Tue, Sep 2 2008
    • Posts 16
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    Stacked via violations in encounter power router. Reply

     I am trying to create the power routes using Encounter 9.1 

    There are lot of memories in the design which has power pins in layer M4  ( design is 8 Metal layer process) i create the stripe in M3 & M7 where in M7 gets tapped to some of the power pins of the memories as the pitch of M7 is such that some of the memory pins does not get over lapped with M7 stripe so those are left open. so i create a sub mesh kind of struture on those memory pins & connect the sub mesh to the stripe in M7 

       During this stage there are lot of Stacked Via Violations are created,

           Can i use any switchs or any settings so that the tool understands the requriment & create the stack vias properlly.

     

    thanks

    deepak.

    • Post Points: 35
  • Thu, Nov 5 2009 12:13 PM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 693
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    Re: Stacked via violations in encounter power router. Reply

    It's hard to say without knowing the specific via stacking rules for your process. Usually, power vias do not trigger via stack violations because the metal is wider and via arrays are used, instead of a single via. Most via stack rules only apply to single vias - arrays do not trigger the violation. Are your power stripes thin enough that you only have one via cut at the intersections? There are some different via stacking keywords available in the LEF file that may help you, but I'm not sure what your paricular violation is. What is flagging the violations? VerifyGeometry, or your signoff DRC tool?

    • Post Points: 20
  • Mon, Nov 9 2009 6:16 AM

    • deeps
    • Top 500 Contributor
    • Joined on Tue, Sep 2 2008
    • Posts 16
    • Points 245
    Re: Stacked via violations in encounter power router. Reply
    Hi Kari,

    I am using verify geometry command to get details of the violations (not Sign off)

     I am not sure the reason for this kind of violations, I got some inputs from Cadence support saying that I need to set some variable before creating the power routes (setvar ALLOWOVERLAPINSTACKVIA true)

    But still there are lot of stacked via violations

    Here the violations are created even with via array,  I am not sure how to get rid of this kind of violations.

    Thanks

    Deepak.,
    • Post Points: 20
  • Mon, Nov 9 2009 12:08 PM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
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    Re: Stacked via violations in encounter power router. Reply

    Hi Deepak,

    Can you paste the exact wording of the verifyGeometry violation along with a picture of the violation?

    - Kari

    • Post Points: 20
  • Mon, Aug 27 2012 2:03 PM

    Re: Stacked via violations in encounter power router. Reply

    Hi Kari,

    I am also seeing below issue ,

     Regular Via of Net design1/mlm_ahb_main_i/FE_OFN86065_sram_main_wdata_298_ & Regular Via of Net design1/mlm_ahb_main_i/FE_OFN86065_sram_main_wdata_298_
    |( VIA5 VIA1 )
    bbox = (2312.905, 1807.365) (2312.975, 1807.435)

     Thanks,

    mnm

     

    • Post Points: 20
  • Tue, Aug 28 2012 6:08 AM

    • Kari
    • Top 10 Contributor
    • Joined on Tue, Jul 15 2008
    • Cary, NC
    • Posts 693
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    Re: Stacked via violations in encounter power router. Reply

    Hi,

     What kind of violation is this? Short? Spacing? A picture would help...

     - Kari 

    • Post Points: 5
  • Fri, Aug 31 2012 12:02 AM

    • snoredpig
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    • Joined on Thu, Aug 30 2012
    • Posts 2
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    Re: Stacked via violations in encounter power router. Reply
    zoom the region and use editPowerVia to delete those vias. and re-generate those vias by editPowerVia by specified area.
    • Post Points: 5
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Started by deeps at 04 Nov 2009 05:36 AM. Topic has 6 replies.