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 Toggle coverage on SystemVerilog interfaces 

Last post Thu, Oct 29 2009 3:55 PM by nlin. 1 replies.
Started by maxb 29 Oct 2009 07:59 AM. Topic has 1 replies and 1483 views
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  • Thu, Oct 29 2009 7:59 AM

    • maxb
    • Not Ranked
    • Joined on Thu, Jan 22 2009
    • Kista, Sweden
    • Posts 9
    • Points 135
    Toggle coverage on SystemVerilog interfaces Reply

    In our design we use interfaces to connect modules. But when running coverage analysis, all signals in the interfaces show 0% toggle coverage, although the signals are clearly toggling in the simulation. How do I get the correct toggle coverage?

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    • Post Points: 20
  • Thu, Oct 29 2009 3:55 PM

    • nlin
    • Not Ranked
    • Joined on Tue, Aug 4 2009
    • Posts 5
    • Points 125
    Re: Toggle coverage on SystemVerilog interfaces Reply

    Hi Max,

    Toggle coverage is not yet supported for SV interfaces. If you email me your contact inf, I can be sure to notify you when support is added.  My email is nlin@cadence.com.

     In the future, if you have questions about the functionality of the tools, be sure to go to support.cadence.com

    Best Regards,

    Nancy

    • Post Points: 5
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Started by maxb at 29 Oct 2009 07:59 AM. Topic has 1 replies.