in a bottomup design flow , there is a submodule,it has its own power ring and stripe,
when load the submodule to top level, how to make toplevel know the submodule's ring and stripe, so when do Sroute, top level row and stripe will hook up the subblock ring and stripe correctly.
the submodule designed by FLAT Encounter flow with a speical digital library, it has IO row, POWR ring/stripe and core row.
right now I use lef2oa and oa2lef, I can see VDD and VSS pin,but I cannot see the RING and Stripe definition.
can somebody show me how to do this