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 bottomup flow,how to make submodule ring and stripe can been see in top module 

Last post Thu, May 16 2013 11:08 PM by meganzluckett. 7 replies.
Started by verysmart 28 Sep 2009 11:21 PM. Topic has 7 replies and 5726 views
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  • Mon, Sep 28 2009 11:21 PM

    • verysmart
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    • Joined on Wed, Jan 14 2009
    • Posts 5
    • Points 85
    bottomup flow,how to make submodule ring and stripe can been see in top module Reply

    in a bottomup design flow , there is a submodule,it has its own power ring and stripe,

    when load the submodule to top level,   how to make toplevel  know the  submodule's ring and stripe, so when do Sroute,  top level row and stripe will hook up the subblock ring and stripe correctly.

      the submodule designed by FLAT  Encounter flow with a speical digital library,  it has IO row, POWR ring/stripe and core row.

    right now I use lef2oa and oa2lef, I can see VDD and VSS pin,but I cannot see the RING and Stripe definition. 

    can somebody show me how to do this

     

      

      

     


    • Post Points: 35
  • Mon, Sep 28 2009 11:59 PM

    • KVBABU
    • Top 500 Contributor
    • Joined on Thu, Jul 23 2009
    • Hyderabad, Andhra Pradesh
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    Re: bottomup flow,how to make submodule ring and stripe can been see in top module Reply

    Hi

    After performing place and route for a block level design, extract a lef for that design using lefOut - command  .

    Ex:  lefOut -stripePin -PGpinLayers block_top_routing_layer  -specifyTopLayer  block_top_routing_layer  -5.6  outputfilename.lef

     

    Use this lef in top level flow along with technolgy lef & physical lef . Then you will get power grid information and it is vissible when you turn on instance pin. The tool will acees the same info while doing top level information.

     

    Regards,

    KVB 

    K.VISWANADH BABU
    • Post Points: 20
  • Tue, Sep 29 2009 12:41 AM

    • verysmart
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    Re: bottomup flow,how to make submodule ring and stripe can been see in top module Reply

     I use :  lefOut -stripePin -PGpinLayers 1 2 -extractBlockPGPinLayers 1 2   sub_block0.lef

      we do Sroute I  add  -stripeSCpinTarget boundaryWithPin option,since there are some space between my ring and block Boundary

    after load into toplevel ,I can see the power row/stripe pin come out is on Metal1 (lef/right) Metal2(top)

    but after  power planing,  see the power row is hook up but with METAL1 ,but it add  METAL3  to hookup the hardmarco follow Power pin(VDD already hook up METAL1,why it add METAL3),   and a lot  open error with the blockwire and followpin 

     

     

    • Post Points: 20
  • Tue, Sep 29 2009 1:19 AM

    • verysmart
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    • Posts 5
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    Re: bottomup flow,how to make submodule ring and stripe can been see in top module Reply

    similar issue on another website:

    http://www.chiptalk.org/modules/newbb/viewtopic.php?topic_id=202&forum=2&post_id=789

     

    Hierarchical place and route with Encounter
    Hi -

    I'm trying to figure out how to place and route a hierarchy with SOC Encounter (v5.2). I must be missing something because it shouldn't be this hard! What I've done is:

    1 - Start by place and routing a core macro. This works fine. I have a vdd! and gnd! ring around the circuit. I generate DEF and Verilog and read this back in to dfII and it DRC's and LVS's just fine. I'd like to use this macro in another design as a pre-designed macro!

    2 - In SOC I use lefOut with the -stripePin option to get a lef file with vdd! and gnd! pins. I also generate a .lib file using do_extract_model. (I've also tried generating the lef file by running abstract on the layout view from dfII - same behavior)

    3 - In SOC in my top-level design I import the core.lef and core.lib files in addition to the other stuff for my top-level design. The core is instantiated in my structural verilog file. When this is imported I get a core block that I can place in the floorplan.

    4 - I can pick up and place the block, put a halo around it, etc. All seems fine...

    5 - HERE'S THE PROBLEM - when I do my power planning (rings and stripes), I can NOT get the power routing connected to this macro! I've tried with the macro as CLASS BLOCK in the lef, I've tried with the macro as CLASS RING in the lef. I've tried making the vdd! and gnd! ports also of CLASS RING. I've made sure that I'm selecting the block pins in sroute. I've even followed the convoluted power planning template flow in the dtmf tutorial included with SOC.

    NOTHING WORKS. The power routing ends up connected to the pads, connected to the standard cell rows, and the stripes are connected to the standard cells rows. But, the stripes just end before they get to my core macro. They don't connect to it!

    It seems as if the nanorouting for the signal pins also works fine. But, I can't get SOC to connect the vdd! and gnd! wires to my macro. This macro was placed and routed by SOC, and the lef and lib were also generated by SOC. It must be possible to use it in SOC!

    Help! What am I doing wrong or what am I not doing that needs to be done to make this work?

    Thanks!
    -Erik
    • Post Points: 5
  • Wed, Oct 7 2009 1:02 PM

    • Kari
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    Re: bottomup flow,how to make submodule ring and stripe can been see in top module Reply

     Are your global nets defined correctly? If you turn on query mode (the Q button at the bottom of the Encounter GUI), and put your mouse over one of your block pwr/gnd pins, does the information at the bottom of the Encounter window show the right net connection? Can you draw a connection by hand without any violations?

    • Post Points: 20
  • Mon, Oct 12 2009 11:38 PM

    • verysmart
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    Re: bottomup flow,how to make submodule ring and stripe can been see in top module Reply
    Hi Kari:

    when I turn on Instance pin, I can see the VDD pin, but Q button doesn't show right info,  while Normal pin in the block shows OK,

    by the way I load the subblock by OpenAccess.
    • Post Points: 20
  • Wed, Oct 14 2009 12:30 PM

    • Kari
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    Re: bottomup flow,how to make submodule ring and stripe can been see in top module Reply

     Sounds like your global nets are not defined correctly. Look up the globalNetConnect command. You'll probably need something like:

    globalNetConnect VDD -type pgpin -pin VDD -all
    • Post Points: 5
  • Thu, May 16 2013 11:08 PM

    Re: bottomup flow,how to make submodule ring and stripe can been see in top module Reply

     hello verysmart. i'm just wondering if this has already been resolved since this has been initially posted way back 2009? if so, hope you can share with us how did you manage it. and if not, just let us know also what are the steps that you have taken already. as we can see, it seems that their has been no update for like three years already so hope you can update us. thanks.

     

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    • Post Points: 5
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Started by verysmart at 28 Sep 2009 11:21 PM. Topic has 7 replies.