I try to run ams simulation with UltraSim solver a block (let's call it A) containing block (B) described as a spice netlist. Block B has several bus inputs and during elaboration I receive error message: "Vector net cannot be connected to a Spice/Spectre instance by port name". Really, netlist of block A has intstance of B: subckt_B B(.OUT(out), .IN(in[3:0])), while spice description of subcircuit B looks like .SUBCKT subckt_B OUT IN<0> IN<1> IN<2> IN<3>. I added cfg file with cell description
string prop sourcefile="path_to_file";
string prop sourcefile_opts="-auto_bus" ;
But it didn't help.
How can I run ams simulation for design, which contains spice netlist with bus ports?