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 ams: simulating design with spice netlist with bus ports 

Last post Mon, Sep 14 2009 5:07 AM by Andrew Beckett. 1 replies.
Started by Runner 14 Sep 2009 05:02 AM. Topic has 1 replies and 2043 views
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  • Mon, Sep 14 2009 5:02 AM

    • Runner
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    • Joined on Fri, May 8 2009
    • Posts 11
    • Points 305
    ams: simulating design with spice netlist with bus ports Reply

    I try to run ams simulation with UltraSim solver a block (let's call it A) containing block (B) described as a spice netlist. Block B has several bus inputs and during elaboration I receive error message: "Vector net cannot be connected to a Spice/Spectre instance by port name". Really, netlist of block A has intstance of B: subckt_B B(.OUT(out), .IN(in[3:0])), while spice description of subcircuit B looks like .SUBCKT subckt_B OUT IN<0> IN<1> IN<2> IN<3>. I added cfg file with cell description

    cell  subckt_B

        string prop sourcefile="path_to_file";

        string prop sourcefile_opts="-auto_bus" ;

     }

    But it didn't  help.

    How can I run ams simulation for design, which contains spice netlist with bus ports?

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    • Post Points: 20
  • Mon, Sep 14 2009 5:07 AM

    Re: ams: simulating design with spice netlist with bus ports Reply

    What you've said sounds as if it's probably reasonable, but it's hard to tell without seeing the whole picture.

    You're probably best off contacting Cadence customer support and providing the data that you're trying to simulate, and then somebody can investigate this more closely than is possible in a public forum.

    Best Regards,

    Andrew.

    • Post Points: 5
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Started by Runner at 14 Sep 2009 05:02 AM. Topic has 1 replies.