Hi Bob,Originally posted in cdnusers.org by EngHan
First to clarify my issue. I should say "high local placement utilization" and not "local congestion". There is no congestion even when with the high local utilizaiton. The local utilization is very high. By eyeball, it is almost (or it is) 100% for more than 10 rows and 30-50 std cell width (I cannot remember exactly, this is my impression).
There is no issue before CTS (so physical synthesis part is okay). Also, I have not perform fix hold, so the problem occur only during CTS.
I study the issue breifly. I think it is due to the tool size-up all the clock gates (CG)r. The design uses RC to insert cg even only when one FF is gated. So the design has 7000+ CG. Before CTS, most of the CG are 2x. After CTS, most of the CG are 12x and 16x. I believe this is causing local congestion.
Now, before you think I have issue with my CTS specification file, I have tried many things. I have used mainly default setting, relaxed setting, and many in-between. I end up disable the high drive CG. It helps some, but not completely.
Now again (:>) before you double my technology, I am using TSMC 0.18um lef, captable (with co-relation with QX), etc etc. This library cannot be that bad, correct?
Back to my observation and feeling. I don't have this issue when I use 4.* and 5.* but for 2 consecutive projects I have this issue. I tend to think there is something in 6.* that make this happen. Of course I can be wrong; I hope to hear from the users of 6.* if they also face the same issue. Also, spread out the cells to ease local congestion is a basic function of the placer. Although all the cells have been placed, and CTS suppose to make minimum movement of the cells, I think something can be done here in an automated way.
By the way, in a previous project I try to use cell/instance padding but it does not seem to be supported anymore by the new moduleplan placer. I am not 100% sure here...