Normally you would use a tool such as Virtuoso Layout XL to perform connectivity driven layout. This will generate layout instances with the same parameters as the corresponding schematic - and has checks in place to ensure that parameters match. You have the ability to deviate in the layout - there may be good reasons for setting some parameters differently on the resulting layout. Similarly, it's possible to have a different hierarchy - you might (for example have hierarchy on the schematic, but not want it on the layout).
SImilarly you might want to have parameter inheritance on the schematic (functions such as pPar), but on the layout you need to "harden" any parameters because in reality your layout needs to be fixed.
So normally you wouldn't have it directly linked between the schematic and layout views of a particular instance - but it is very easy with Layout XL to update your layout to match the schematic.
In general I suggest that people have pcells with parameters which are the same parameters you would use for simulation - so these may be electrical (although with MOSFETs they're often physical - width and length), and then the pcell is responsible to transform them into physical dimensions. As long as what you simulate is consistent with what your layout generates, and you can verify that, you're fine. In general you want all views to be driven from the same set of parameters - the danger of CDF callbacks is that if you have (say) pcell parameters derived from the parameters you enter on the schematic, and you simulate using the entered parameters, there's a risk that the callbacks didn't trigger, and so you are laying out something different to that which you simulated. If you're not careful you can end up LVSing the layout against the derived parameters, so you never know that what you laid out is not what you simulated... (more on this in the solution I mentioned).