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 test to write and read registers with field order like packing.low 

Last post Fri, Sep 4 2009 3:10 AM by StephenH. 1 replies.
Started by mkyang 27 Aug 2009 02:26 AM. Topic has 1 replies and 1794 views
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  • Thu, Aug 27 2009 2:26 AM

    • mkyang
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    • Joined on Wed, Nov 5 2008
    • Posts 1
    • Points 20
    test to write and read registers with field order like packing.low Reply

    Hi,

    Please, tell me how to test registers when the filed order of a register is packing.low, from a low bit position to a high bit position.

    I applied the following code by referencing the document 'The Register and Memorr Model', but I could not get correct result.

    extend MY_REG vr_ad_reg_file {

    keep packing_mode == packing.low;

    };

    extend MAIN vr_ad_sequence {

    !rgf_seq : ALL_REGS_IN_FILE vr_ad_sequence;

    body() @driver.clock is {

    ...

    do rgf_seq keeping {

    .reg_file == MY_REG;

    .order == ASCENDING;

    .direction == WRITE

    };

    ...

    };

    But, it seems not writing values correctly to registers.

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    • Post Points: 20
  • Fri, Sep 4 2009 3:10 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 278
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    Re: test to write and read registers with field order like packing.low Reply

    This should work, but applies to an entire register file, not individual registers (looks like you knew that already, but I thought it was worth mentioning).

    It's impossible to know what's wrong from your description. Can you give more detail about the symptoms?
    You say that "[vr_ad is] not writing values correctly to the registers"; can you provide a concrete example please?

    1. What values do the individual fields show in the vr_ad_reg when it's generated by the sequence?

    2. What is the hex value of the bus data when vr_ad_execute_op() is called?
      Hint: set a break point on the vr_ad_execute_op() method in your bus eVC's hook-up file.

    3. Does the vr_ad hook-up to your bus eVC handle the data correctly?

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
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    • Post Points: 5
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Started by mkyang at 27 Aug 2009 02:26 AM. Topic has 1 replies.