In our design, we instantiate a library clock gating cell ("DLSG1") to do functional clock gating at the RTL level. This cell has an SE input which is left unconnected in the RTL code since no other DFT signals are present at this stage:
module my_cg (input clk, input enable, output clk_gated);
DLSG1 u_cg (.C (clk), .E (enable), .SE (), .GCK (clk_gated));
How can I connect the SE input of this cell to the shift_enable signal which is defined during synthesis?
I have defined scan chains and test control signals at the top level, but when I run check_dft_rules I get warnings that the clock is not controllable:
Warning : DFT Clock Rule Violation. [DFT-301]
: # 0 <vid_0_clock>: internal or gated clock signal in module 'my_cg', net 'clk_gated', inst/pin '.../my_cg/GCK' [CLOCK-05]
: Clock signal is not controllable. Affected registers will be excluded from scan design.