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 How do I connect an instiantiated library clock gating cell to scan chains? 

Last post Wed, Sep 2 2009 2:08 AM by Henry Wang. 1 replies.
Started by maxb 25 Aug 2009 06:55 AM. Topic has 1 replies and 2441 views
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  • Tue, Aug 25 2009 6:55 AM

    • maxb
    • Not Ranked
    • Joined on Thu, Jan 22 2009
    • Kista, Sweden
    • Posts 9
    • Points 135
    How do I connect an instiantiated library clock gating cell to scan chains? Reply

    In our design, we instantiate a library clock gating cell ("DLSG1") to do functional clock gating at the RTL level. This cell has an SE input which is left unconnected in the RTL code since no other DFT signals are present at this stage:

    module my_cg (input clk, input enable, output clk_gated);

       DLSG1 u_cg (.C (clk), .E (enable), .SE (), .GCK (clk_gated));
    endmodule

    How can I connect the SE input of this cell to the shift_enable signal which is defined during synthesis?

    I have defined scan chains and test control signals at the top level, but when I run check_dft_rules I get warnings that the clock is not controllable:

    Warning : DFT Clock Rule Violation. [DFT-301]
            : # 0 <vid_0_clock>: internal or gated clock signal in module 'my_cg', net 'clk_gated', inst/pin '.../my_cg/GCK'   [CLOCK-05]
            : Clock signal is not controllable. Affected registers will be excluded from scan design.

    • Post Points: 20
  • Wed, Sep 2 2009 2:08 AM

    • Henry Wang
    • Not Ranked
    • Joined on Fri, Jul 18 2008
    • Markham, Ontario
    • Posts 1
    • Points 10
    Re: How do I connect an instiantiated library clock gating cell to scan chains? Reply
    Synthesis tool will not hook up hand instantiated gater SE pin for you. You have to do it manually in RTL. Or, you can write a TCL script to hook up SE pin during synthesis, but not suggested, cause you need constraints shift enable when running LEC.
    • Post Points: 5
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Started by maxb at 25 Aug 2009 06:55 AM. Topic has 1 replies.