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 Monte Carlo simulation 

Last post Wed, Aug 26 2009 2:57 AM by Andrew Beckett. 3 replies.
Started by whlinfei 20 Aug 2009 12:10 AM. Topic has 3 replies and 2791 views
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  • Thu, Aug 20 2009 12:10 AM

    • whlinfei
    • Top 500 Contributor
    • Joined on Sun, Mar 15 2009
    • Posts 24
    • Points 435
    Monte Carlo simulation Reply

    Dear All,

     I have the schematic of a current matching circuit. I want to test how well the matching is using Monte Carlo simulation?

    However I couldn't find it in Spectra analysis panel.

    Can anyone help me with it? Or provide any other solution to find out how the matching will be in the layout simulation or in the real fabrication?

    thanks  a lot.  I use IBM 130nm process.

     Best Regards,

    Linfei 

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    • Post Points: 20
  • Thu, Aug 20 2009 5:18 AM

    Re: Monte Carlo simulation Reply

    In IC5141, you need to do Tools->Monte Carlo from the ADE window. You can then (on this form) specify the Analysis Variation as Process Only, Mismatch Only or Process & Mismatch.

    In IC612/IC613 you need to start ADE XL. Within ADE XL, you set the Run Mode to "Monte Carlo Sampling" and in the Run Options you can select Process, Mismatch or All.

    You should be able to read up on this in the documentation (cdsdoc in IC5141, cdnshelp in IC61).

    Best Regards,

    Andrew.

    • Post Points: 20
  • Sat, Aug 22 2009 8:59 PM

    • whlinfei
    • Top 500 Contributor
    • Joined on Sun, Mar 15 2009
    • Posts 24
    • Points 435
    Re: Monte Carlo simulation Reply

    Hi Andrew,

    Thanks for your reply.

    I tried out the Mone Carlo simulation as you mentioned. The simulation worked but the result seems unrepresenting the matching performance.

    I think I might dig into the manual to find out the matching specifications of the process I use.

    I am new to this so can you kindly tell me where I might be looking for to find such info?

    I am design a current protection circuit in which I want to used a smaller NMOS to mirror the current going through the power transistor. In the schematic simulation, I manage to get the sampling current to be 1/60 of the current going through power mosfet. But I am not sure that when it comes to fabrication, will this 1/60 would be possible to achieve?

    thanks .

     Best Regards,

    Linfei

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    • Post Points: 20
  • Wed, Aug 26 2009 2:57 AM

    Re: Monte Carlo simulation Reply
    Hi Linfei,

    It's rather hard for me to point you at where in the PDK/model documentation it covers this since I don't have access to the IBM PDK. Better for you to ask your technology provider (IBM?).

    Are you seeing any variation at all if you use "mismatch only"? If not, it may be that you're not using the right set of models; for mismatch the models need to be within subckts. There's a good explanation of this both on sourcelink and www.designersguide.org (I think in the modelling section) in a paper of monte carlo modelling.

    Regards,

    Andrew
    • Post Points: 5
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Started by whlinfei at 20 Aug 2009 12:10 AM. Topic has 3 replies.