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 set a random input data 

Last post Sun, Jul 12 2009 10:07 AM by kamel. 5 replies.
Started by kamel 10 Jul 2009 02:02 PM. Topic has 5 replies and 5559 views
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  • Fri, Jul 10 2009 2:02 PM

    • kamel
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    set a random input data Reply

    hi

    did anybody know how to enter a random input data to perform a simulation using spectre (eg 1101...)

    thank you

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    • Post Points: 20
  • Fri, Jul 10 2009 7:33 PM

    • tkhan
    • Top 50 Contributor
    • Joined on Sat, Aug 16 2008
    • Toronto, Ontario
    • Posts 159
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    Re: set a random input data Reply

    you can use rand_bit_stream from ahdlLib or vsource from analogLib. with vsource its not actually random, you can define the pattern arbitrarily.

    Pattern parameters:
    45      data              The bit string. A string that contains a series of the four states, 1 0 m z.
    46      rptstart=1        The starting bit when repeating. The data repeats from the specified bit to the end of the bit string. The parameter should be an integer from 1 to the length of the bit string.
    47      rpttimes=0        The repeat times. The output will maitain the state of the last bit after the last repeat. If its value is negative, the string repeats forever.
     

    • Post Points: 35
  • Sat, Jul 11 2009 12:57 AM

    Re: set a random input data Reply
    Actually the vsource in spectre now supports a new type, prbs, which produces a pseudo-random bit stream.

    The vsource component in analogLib has not yet been enhanced to support this though. There's an enhancement request for that though.

    Regards,

    Andrew
    • Post Points: 5
  • Sat, Jul 11 2009 10:06 AM

    • kamel
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    Re: set a random input data Reply

     thank you all i appreciate

    unfortunetly it doesnt't work with the version of spectre i have, it expect a 6.2 or later.

     i think it's possible to write a module in Verilog -ams that's supports rhe generation of a sequence of bit, but how to include it ?

    regards,

    kamel

    • Post Points: 20
  • Sun, Jul 12 2009 12:36 AM

    Re: set a random input data Reply
    Kamel,

    The rand_bit_stream in ahdlLib should work whatever version you're using. It's been there for at least 10 years, and is a Verilog-A model that you can always customize if it doesn't meet your needs.

    Regards,

    Andrew
    • Post Points: 20
  • Sun, Jul 12 2009 10:07 AM

    • kamel
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    Re: set a random input data Reply

    thanks Andrew

    i was talking about vsource i tried it and i got an error message according to the version of spectre that i m using.

    regards kamel

    • Post Points: 5
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Started by kamel at 10 Jul 2009 02:02 PM. Topic has 5 replies.