Hi Manzur,
I think it is highly advisable to preserve all the clock network (tree) once you have satisfied CTS results .
Aside the good tcl from li siang for only FF`s ( Does your CTS covers all FF's in your desing ??), i recommend to use .
#-- Change clock status (PLACED -> FIXED)
changeClockStatus -clk FE_CTS_ROOT/Z -fixedBuffers -fixedNetWires -useClock
NOTE : useClock switch has special treatment in routing ( if you specify special attributes like extra space ,top metal layers etc..)
like Ex .
#-- Clock routing
setAttribute -net {@CLOCK} -weight 20 -preferred_extra_space 1
FYI.
-fixedBuffers
Changes the placement status of buffers, inverters, flip-flops, and gating cells from PLACED to FIXED.
-fixedLeafInst
Changes the placement status of leaf instances from PLACED to FIXED.
-fixedNetWires
Changes status of wires in clock nets from ROUTED to FIXED.
-fixedNonLeafInst
Changes the placement status of non-leaf instances from PLACED to FIXED
With Regards,
CH.MOHAN KUMAR
Originally posted in cdnusers.org by mohanch007