Hi Eng Han,
That is the point! In my case the average power is very low because of very long period. Please, consider figure 1.
I think there are switching activity only in a period equal to the critical delay within a clock period. The average current and so the IR drop during this critical delay period will be higher than the average IR drop over the entire clock period. So, this higher IR drop during this short period can provoke timing violations.
Is a good practice to consider a clock period equal the critical delay only to evaluate this effect (not for power estimation)?