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 Clock Generation in NC-VHDL & NC-VERILOG 

Last post Thu, Apr 23 2009 8:43 PM by murali418. 2 replies.
Started by murali418 21 Apr 2009 04:13 AM. Topic has 2 replies and 4322 views
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  • Tue, Apr 21 2009 4:13 AM

    • murali418
    • Not Ranked
    • Joined on Mon, Apr 20 2009
    • Posts 2
    • Points 25
    Clock Generation in NC-VHDL & NC-VERILOG Reply

    Hi All,

    We have clock generation block in one module. The actual code in VHDL is like this


    VHDL  :::::::::

     Clk_1M_s_p : process
      begin
        Clk_1M_s <= '0';
        wait for 0.5 us ;
        Clk_1M_s <= '1';
        wait for 0.5 us ;
      end process Clk_1M_s_p;
     

    VERILOG ::::::::::::::::

    timescale 1fs/1fs

            always  begin : Clk_1M_s_p
                    Clk_1M_s <= 'b0;
                    #(0.5 * 1000_000_000) ; // MicroSeconds
                    Clk_1M_s <=  1'b1;
                    #(0.5 * 1000_000_000) ; // MicroSeconds
            end // Clk_1M_s_p;

     

    When we have compared both the clocks in the Waveform in Simvison we are getting very minute difference which we cannot expand

    through zoom options. When expanded through expancd-at time option. we found there is difference in event scheduling.

     Because of this generation, few events which depends on this clock is delayed and we are getting different results in VERILOG when compared to VHDL.

    Thanks in Advance

    Murali

     

     


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    • Post Points: 20
  • Wed, Apr 22 2009 5:18 PM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 278
    • Points 4,450
    Re: Clock Generation in NC-VHDL & NC-VERILOG Reply
    This is normal, and is due to the way event-based simulation works, especially across HDL language boundaries.
    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 20
  • Thu, Apr 23 2009 8:43 PM

    • murali418
    • Not Ranked
    • Joined on Mon, Apr 20 2009
    • Posts 2
    • Points 25
    Re: Clock Generation in NC-VHDL & NC-VERILOG Reply

    Hi Stephen, Thanks for the reply.

    Actually, because of the scheduling of the event we are getting some extra transactions in Verilog.

    Is there a way to sort out this or else we have  to live with this.

     

     

    Thanks in Advance

    Murali Krishna.Y

    • Post Points: 5
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Started by murali418 at 21 Apr 2009 04:13 AM. Topic has 2 replies.