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 PDK vs. Standard Cell Library 

Last post Tue, Mar 31 2009 3:33 PM by Austin CAD Guy. 1 replies.
Started by weiz 30 Mar 2009 11:05 PM. Topic has 1 replies and 4024 views
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  • Mon, Mar 30 2009 11:05 PM

    • weiz
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    • Joined on Mon, Jul 14 2008
    • Posts 5
    • Points 100
    PDK vs. Standard Cell Library Reply

    Hello,

    I have a question regarding the differences between a PDK/CDK (Process/Cadence Design Kit) and a standard cell library. Sometime people use them interchangeably, but I think there are some inherent differences between these two things. Can anyone clarify this?

    The reason I asked this question is because recently I began searching for a MOSIS compatible 130nm or 90nm process for Cadence to do custom IC layout. I personally used GPDK and NCSU before; they have layout/schematic/symbol views for nmos, pmos, metal1-9, vias, nwell, psub... basically components that let users to build a circuit. However, GPDK is not MOSIS compatible and NCSU does not have 130nm or 90nm processes. I recently obtained IBM cms9flp process ARM Standard Cell Library, however, I don't know how to install it with Cadence. For GPDK or NCSU, there is a "lib" folder that contains all the components and their views (for example, lib/nmos/Layout, lib/nmos/Schematic...). However, there is no such thing for the ARM Standard Cell Library I obtained. Is this one of the differences between PDk and Standard Cell Library. Can anyone explain? I am wondering if I should be looking for cms9flp IBM PDK instead of the Standard Library.

    Thank you all in advanced!

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    • Post Points: 20
  • Tue, Mar 31 2009 3:33 PM

    Re: PDK vs. Standard Cell Library Reply

    A PDK includes the technology data, the base devices, DRC and LVS decks, model files, etc. The CDK (complete design kit) usually is a PDK with digital standard cell libraries. The stdCellLibraries include .lib file (timing) Verilog, .LEF ( Library Echange Format ), GDS - physical layout and some other files are used for place and route.  The LEF is input (LEFin) to create the abstracts, the symbols (VerilogIn) and the layout (GDS). Once these are input, you will have your stdCell library.

    • Post Points: 5
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Started by weiz at 30 Mar 2009 11:05 PM. Topic has 1 replies.