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 compiled eVCs not connected by e-top  

Last post Tue, Mar 31 2009 1:26 AM by StephenH. 1 replies.
Started by Heho 28 Mar 2009 05:09 AM. Topic has 1 replies and 1125 views
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  • Sat, Mar 28 2009 5:09 AM

    • Heho
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    compiled eVCs not connected by e-top Reply

     Hello,

    I am using Specman together with an HDL simulator. I am trying to load two compiled eVCs not to be connected by a single e-top. The goal is to let each one of them access the same HDL DUT at the same time.

    I don't know how to use SPECMAN_DLIB to do this?

     

    Thanks,

    H.K.

    • Post Points: 20
  • Tue, Mar 31 2009 1:26 AM

    • StephenH
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    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
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    Re: compiled eVCs not connected by e-top Reply

    I don't think this is possible. The output from sn_compile.sh is a *.esv and *.so file. These are tightly linked; you can't use one without the other. If you have two eVCs, for example vr_ad and vr_axi, and you compiled them separately, you'd get the following files:
    vr_ad_top.esv, libsn_vr_ad_top.so, vr_axi_top.esv, libsn_vr_axi_top.so

    When you invoke your simulator using SPECMAN_DLIB=libsn_vr_ad_top.so, this also causes the vr_ad_top.esv to be read in, to restore the state of Specman.Now, maybe one of the Specman R&D gurus mightknow better, but I think there's no way to merge or load two *.esv files at the same time, even if you could merge the *.so files.

    Having said all of that, I can't see why you would want to do this anyway. Can you explain why you can't (or don't want to) have a single e top file that gets compiled? Normally we define a fake "top" file that imports all the eVCs needed by the testbench, so that we can compile that file without having to compile the testbench. The following blog post has a good description of this approach: http://www.cadence.com/Community/blogs/fv/archive/2009/03/19/import-guidelines-for-e-part-1.aspx

    You can also do incremental compilation, whereby the results of the 1st compile are rolled into the 2nd, etc. That can be useful where you want to compile your mature / external eVCs for speed, but still run a loaded testbench for debug. You can compile all the mature eVCs in one step, then do another compile step to compile the whole testbench for regression performance. Because you have the intermediate compile result, you can then still run with the loaded testbench.

    Give us some better idea of the problem you are trying to solve, and we'll see if there's a way to do it! :-)

    Regards,
    Steve.

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
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Started by Heho at 28 Mar 2009 05:09 AM. Topic has 1 replies.