Home > Community > Forums > RF Design > pnoise jitter for PLL


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 pnoise jitter for PLL 

Last post Mon, Mar 23 2009 8:19 AM by DZhu. 0 replies.
Started by DZhu 23 Mar 2009 08:19 AM. Topic has 0 replies and 2322 views
Page 1 of 1 (1 items)
Sort Posts:
  • Mon, Mar 23 2009 8:19 AM

    • DZhu
    • Not Ranked
    • Joined on Wed, Nov 26 2008
    • Posts 3
    • Points 30
    pnoise jitter for PLL Reply


    I use "Pnoise jitter" to get the Jee of a PLL. The reference frequency is 20MHz, and the divider ratio is 8, (VCO frequency 160MHz). I use 1kHz as the integration lower limit, is that right? What is the integration upper limit?  Is it fvco/2 = 80MHz? There are spurs at 20MHz, 40MHz and 60MHz. If the integration includes these spur frequencies, how does the infinite flick noise at these points affect the integration results?

    Another question is :

    When I simulate a free running VCO with Pnoise jitter analysis, the four function in the Direct Plot Form below Pnoise jitter are pnoise, -20dB..., Jc and Jcc. When I simulate a PLL, the four functions differ. There is no pnoise. What should I do if I want to look at the pnoise?

    Filed under:
    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by DZhu at 23 Mar 2009 08:19 AM. Topic has 0 replies.