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 Unmapped point (not-mapped) in (R) 

Last post Tue, Aug 30 2011 2:41 AM by Aruna chowdary. 2 replies.
Started by artoo 10 Mar 2009 06:48 PM. Topic has 2 replies and 5000 views
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  • Tue, Mar 10 2009 6:48 PM

    • artoo
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    • Joined on Wed, Dec 10 2008
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    Unmapped point (not-mapped) in (R) Reply

    What does it means when Conformal finds an unmapped point that exists in the revised file (netlist) but not in the golden file (rtl)?

    E.g. here is my message:

    Unmapped point (not-mapped):
      (R)   1516   DFF  ... hierarchy... /ic_addr_reg_22/U$1

     

    I see the always block case statement in the rtl for ic_addr_reg so it exists in rtl, and other similar structures exist which don't cause the same problem.

       always @(posedge ClkIn)
         casez({clk_qual, m_state, ic_update_addr})
           {1'b0, 4'b????,           1'b?} : ic_addr[31:3] <= #1 ic_addr[31:3] ;
           {1'b1, _M_READ_IC_ADDR,   1'b?} : ic_addr[31:3] <= #1 dma_rf_rd_data[31:3] ;
           {1'b1, _M_REREAD_IC_ADDR, 1'b?} : ic_addr[31:3] <= #1 dma_rf_rd_data[31:3] ;
           {1'b1, _M_DMA_WAIT,       1'b1} : ic_addr[31:3] <= #1 ic_addr[31:3] + 29'h1;
           default                         : ic_addr[31:3] <= #1 ic_addr[31:3];
         endcase
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    • Post Points: 35
  • Wed, Mar 11 2009 10:42 AM

    • croy
    • Top 500 Contributor
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    Re: Unmapped point (not-mapped) in (R) Reply

     Hi artoo

     

    I would do 'report message -model -golden -verbose > model.rpt', to see what's happening to that flop on the golden side during modeling.

     

    Chrystian

    • Post Points: 5
  • Tue, Aug 30 2011 2:41 AM

    • Aruna chowdary
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    • Joined on Tue, Aug 30 2011
    • bangalore, Karnataka
    • Posts 1
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    Re: Unmapped point (not-mapped) in (R) Reply

    Hi, the conformal gives those un mapped points because when it compares golden(rtl) and schematic(revised), if the pins or any Black box modules are not matched from both sides...   The reason could be : If that pin is an input or output pin at the top level :  After abstract logic of schematic, we may get a signal which is only one direction pin where as in rtl it might be bi directional. so please check the pin dimensions on both(see the schematics of both)

    Try to check by black boxing every module and try to run it once, so that we can find the source of error easily..

    Also try with not doing the abstract logic of schematic, some times tool will give some un mapped points if it is unable to map due to black boxing...

    Let me know if i am not clear..

    Regards..

     

     

     

    • Post Points: 5
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Started by artoo at 10 Mar 2009 06:48 PM. Topic has 2 replies.