Originally posted in cdnusers.org by elvis
1. Can NanoRoute Ultra handle a problem of this nature? Can it give an efficient solution or is it not really tuned for such problems?
>>> That is a lot of memories design and I do not have the experience with that quantity. I would suggest running trial route first to make sure congestion issues are solved at the global route (floorplan) phase rather than wait for the detail routes. I have routed a design with Nanoroute that has 300+ memories with similar amount of memory pins without a problem.
2. What input format of the design does the router require? Are there any restrictions on where the pins of each block should be located? Is the router capable of using metal layers that have been utilized within a block layout?
>>> The input to nanoroute is DEF. I'm not sure about utilizing metal layers within the block. My guess is that since the LEF abstract is modeled as routing blockage that this is not possible. Maybe if you use GDS? Just a guess.
3. Can the router also add buffering for high fanout/long nets? Can it make use of preplaced buffers?
>>> This step is done by optDesign during physical synthesis. I don't think nanoroute will add buffers, though during SI repair nanoroute will work with Celtic in SoC-E to automatically insert buffers to eliminate SI issues.
Hope this helps.