Home > Community > Forums > Digital Implementation > Routing of large number of preplaced blocks

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Routing of large number of preplaced blocks 

Last post Tue, Feb 14 2006 9:52 PM by archive. 1 replies.
Started by archive 14 Feb 2006 09:52 PM. Topic has 1 replies and 1128 views
Page 1 of 1 (2 items)
Sort Posts:
  • Tue, Feb 14 2006 9:52 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    Routing of large number of preplaced blocks Reply

    Hi,

    I have a problem in which I need to route a large number (around 1000) of logic and memory blocks in a structured ASIC. Each logic block may have variable number of inputs and outputs (around 40 I/Os) that need to be routed. Each of the memory blocks has around 90-100 I/Os. Here are my questions:

    1. Can NanoRoute Ultra handle a problem of this nature? Can it give an efficient solution or is it not really tuned for such problems?

    2. What input format of the design does the router require? Are there any restrictions on where the pins of each block should be located? Is the router capable of using metal layers that have been utilized within a block layout?

    3. Can the router also add buffering for high fanout/long nets? Can it make use of preplaced buffers?

    Thanks very much. Greatly appreciated.


    Originally posted in cdnusers.org by cdnuser78
    • Post Points: 0
  • Wed, Feb 15 2006 11:28 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: Routing of large number of preplaced blocks Reply


    Hi CDNUser78,

    1. Can NanoRoute Ultra handle a problem of this nature? Can it give an efficient solution or is it not really tuned for such problems?

    >>> That is a lot of memories design and I do not have the experience with that quantity. I would suggest running trial route first to make sure congestion issues are solved at the global route (floorplan) phase rather than wait for the detail routes. I have routed a design with Nanoroute that has 300+ memories with similar amount of memory pins without a problem.

    2. What input format of the design does the router require? Are there any restrictions on where the pins of each block should be located? Is the router capable of using metal layers that have been utilized within a block layout?

    >>> The input to nanoroute is DEF. I'm not sure about utilizing metal layers within the block. My guess is that since the LEF abstract is modeled as routing blockage that this is not possible. Maybe if you use GDS? Just a guess.

    3. Can the router also add buffering for high fanout/long nets? Can it make use of preplaced buffers?

    >>> This step is done by optDesign during physical synthesis. I don't think nanoroute will add buffers, though during SI repair nanoroute will work with Celtic in SoC-E to automatically insert buffers to eliminate SI issues.

    Hope this helps.

    Elvis


    Originally posted in cdnusers.org by elvis
    • Post Points: 0
Page 1 of 1 (2 items)
Sort Posts:
Started by archive at 14 Feb 2006 09:52 PM. Topic has 1 replies.