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 Profiling the runtime of SystemVerilog Assertions 

Last post Fri, Jan 16 2009 10:27 AM by danlarkin. 4 replies.
Started by danlarkin 15 Jan 2009 02:29 AM. Topic has 4 replies and 2763 views
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  • Thu, Jan 15 2009 2:29 AM

    • danlarkin
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    Profiling the runtime of SystemVerilog Assertions Reply

    Hi all,

    I'm concerned that a collection of assertion based checkers that I'm using are causing a dramatic slow down in the run time of my simulation. My hunch is that  the widespread use of multiple internal variables in some of the assertions are using vast amounts of memory and are thus negatively impacting the run time of the overall simulation.

    How do I go about debugging such an issue? For example, I remember hearing that Incisive 8.2 was to have the ability to profile assertions - however when I tried out 8.20-p001 (and added the -profile option) I don't seem to be getting any additional profile information in the profile logfile?

     Any pointers o0r recommendations would be most appreciated.

    Thanks

    Daniel 

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  • Thu, Jan 15 2009 2:39 AM

    • Shalom B
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    Re: Profiling the runtime of SystemVerilog Assertions Reply

    I got a similar report from one of my users. I asked him to run with profiler but he never got back to me.  Shalom

    Shalom.Bresticker@intel.com
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  • Thu, Jan 15 2009 8:54 AM

    • ckomar
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    Re: Profiling the runtime of SystemVerilog Assertions Reply

    Hi Daniel,

     You are correct. This feature was added in version 8.2. I just tried it on a simple testcase that I have and get the following in my ncprof.out.  Are you not seeing a section in the log file that looks something like this?

    ------------------------------------------------------------
    Assertion Summary Counts (15 hits, 28.8% of total)
    ------------------------------------------------------------
    %hits #hits  #inst  name
      7.7     4 [    1] input_Done_and_Gnt (assert stmt, file: ../vcomp/vcomp_arb.v, line: 27)
      3.8     2 [    1] output_GntA_then_Busy_overlaps_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 65)
      3.8     2 [    1] output_Gnt_onehot0 (assert stmt, file: ../vcomp/vcomp_arb.v, line: 40)
      3.8     2 [    1] input_Gnt_eventually_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 23)
      3.8     2 [    1] input_ReqB_and_GntB (assert stmt, file: ../vcomp/vcomp_arb.v, line: 17)
      3.8     2 [    1] input_ReqA_and_GntA (assert stmt, file: ../vcomp/vcomp_arb.v, line: 15)
      1.9     1 [    1] output_GntB_then_Busy_overlaps_Done (assert stmt, file: ../vcomp/vcomp_arb.v, line: 67)

    Chris

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  • Thu, Jan 15 2009 1:44 PM

    • tpylant
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    Re: Profiling the runtime of SystemVerilog Assertions Reply

    In addtion to what Chris showed, you will also get this information (copied from Assertion Checking in Simulation manual):

    In addition to the basic profiling improvements, which will be useful for diagnosing almost any performance problem, warnings will identify certain problems more specifically. These warnings will provide some indication as to why some assertions might be particularly slow, so that the user can improve them, including:

    • Large number of attempts in flight, indicating that the enabling condition might be too permissive, or that old attempts never completed
    • Large number of false starts, when an inactive property is activated, tests its data, and goes becomes inactive again
    • Continually increasing memory usage

    If profiling is enabled, these warnings are included in the simulation log file, once per affected assertion.
    These warnings also appear as part of the profile report, following the Assertion Summary section, so that they can be analyzed without the need to cross-reference the profile report against the simulation log file. 

    Tim

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  • Fri, Jan 16 2009 10:27 AM

    • danlarkin
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    Re: Profiling the runtime of SystemVerilog Assertions Reply

    Thanks Tim and Chris, thats really useful information! I must say there is some very good SVA documentation now with Incisive 8,2  (not sure what version this documentation arrived with, but I know it wasn't there a year ago or at least i wasn't aware of it then).

    The reason I didn't see the profiling information is that all the properties are in an off state (which I believe is due to an $assertoff or $assertkill - despite the fact I can't find any). Interestingly whatever is causing this wasn't a problem in 6.2-s4.

     

    Anyway , when I do get round to resolving this, I may follow up with a further question about assertion profiling/performance.

    Thanks again for the very useful pointers - much appreciated!

    Daniel 

     

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Started by danlarkin at 15 Jan 2009 02:29 AM. Topic has 4 replies.