Home > Community > Forums > Digital Implementation > How to preserve logical function at hierarchical ports after some timing optimizations done with setOptMode -preserveModuleFunction false.

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 How to preserve logical function at hierarchical ports after some timing optimizations done with setOptMode -preserveModuleFunction false. 

Last post Wed, Jan 14 2009 11:17 AM by dlferrao. 0 replies.
Started by dlferrao 14 Jan 2009 11:17 AM. Topic has 0 replies and 1449 views
Page 1 of 1 (1 items)
Sort Posts:
  • Wed, Jan 14 2009 11:17 AM

    • dlferrao
    • Not Ranked
    • Joined on Mon, Sep 15 2008
    • Porto Alegre, Rio Grande do Sul
    • Posts 6
    • Points 55
    How to preserve logical function at hierarchical ports after some timing optimizations done with setOptMode -preserveModuleFunction false. Reply

     Hi There,

    I have an issue regarding setOptMode -preserveModuleFunction false.
    I have set this option to false, so FE will do optimization disregarding if logical function changes occur at hierarchical output ports.

    One example of this is splitting an inverter pair across hierarchy boundaries.

    But *now*, my verification guys want me to preserve the logic function at module output ports.
    I don't want to go back before any timing optimization perform all optimization again with the -preserveModuleFunction true.

    Is there a way to fix it in a design after optimization have been done?

    I was thinking in some script that detect some split inverter pair and change the inverters name to be inside the same module hierarchy.

    Someone has faced some similar problem?

    Thanks!

    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by dlferrao at 14 Jan 2009 11:17 AM. Topic has 0 replies.