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 Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? 

Last post Tue, May 21 2013 8:52 AM by ScottCad. 15 replies.
Started by EE92780 30 Sep 2008 12:12 PM. Topic has 15 replies and 12491 views
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  • Tue, Sep 30 2008 12:12 PM

    • EE92780
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    Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    Can anyone please explain the difference between "Place_Bound_Top" "Dfa_Bound_Top" and "Package_Keepout_Top?"  When using the built in package wizard, it seems to create an identical shape for the Place and Dfa bound tops.  So why have two?  How do these differ fundamentally from the package keepout area?  Thanks!!!

    • Post Points: 95
  • Tue, Sep 30 2008 12:37 PM

    • mcatramb91
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    RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply
    Place_Bound_Top
    Used to ensure you don’t place components on top of each without getting a DRC.  This boundary
    normally defines the component area which may or may not include pins of surface mount devices.
    This boundary can also be assigned a component high to be verified at the board level and checked
    to the Package_Keepout_Top boundaries or any other special component clearances.  If this boundary
    does not exist than it will be automatically created based on the Assembly_Top outline and the outer
    extents of the component pins. This boundary can only be defined at the symbol level (.dra).
     
    Dfa_Bound_Top
    Used by the Real Time Design for Assembly (DFA) Analysis to check clearances between components
    driven by a Spreadsheet based matrix of components.  This boundary normally or can be different then
    the traditional Place_Bound_Top boundary and it may include pins of surface mount devices.
    If this boundary does not exist than the DFA checks default to using the Place_Bound_Top boundary.  
    This boundary can only be defined at the symbol level (.dra).

    Package_Keepout_Top
    Used to ensure you don’t violate placement keepout areas or high restricted area in a design.
    This boundary can only be defined at the board level (.brd) and cannot be added to the
    symbol level (.dra) unless it is part of a Mechanical Symbol (.bsm)

    Hope this helps,
    Michael Catrambone
    UTStarcom, Inc.
    • Post Points: 5
  • Wed, Oct 8 2008 7:39 AM

    • lcanx2
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    RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply
    2 questions.

    1)      Can you really not build a symbol to include a package_keepout_top or am I misreading the reply?

    2)      CADENCE states in their help that the Dynamic DFA for component clearances is not available while in the “Edit Move” command, only the “Place Manual” command.  Do other users see the advantage of having Dynamic DFA checking available to them regardless of what command is being used to move a symbol?

    >Package_Keepout_Top

    >Used to ensure you don’t violate placementkeepout areas or high restricted area in a design.  

    >This boundary can only be defined at the boardlevel (.brd) and cannot be added to the symbol level (.dra)

    >unless it is part of a Mechanical Symbol(.bsm)
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  • Wed, Oct 8 2008 7:56 AM

    • mcatramb91
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    Re: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    Yes that is correct.  PACKAGE_KEEPOUT_TOP can only be defined at the board level (.brd) and it is used to prevent components from being placed in a particular area of design and in some cases a particular height.  The only exception is PACKAGE_KEEPOUT_TOP can be added to a Mechanical Symbol (.bsm).  A mechanical symbol is used to generate a master Board Outline, Keepouts and Keepin for a design which is generated the same way a package symbol (component) is generated but with a mechanical symbols you have the ability to add PACKAGE_KEEPOUT_TOP to it during creation.  Most people do not use Mechanical Symbols for their Master Board Outline symbol anymore and instead use a Master Layout (.brd) which contains the master board outline which was generated at the Layout level (.brd)

    YES I do see a benefit of having the Dynamic DFA for component clearances available during Edit Move.  I thought I heard that this functionality was coming in a future release at this past CDNLive! but I may be mistaking.

    Hope this helps,
    Michael Catrambone
    UTStarcom, Inc.

    • Post Points: 5
  • Wed, Oct 8 2008 10:13 AM

    • lcanx2
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    RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply
    Hi Mike,

    I have to respectfully disagree.  I have added Package Keepout Top (as well as Bottom) to non-mechanical symbols without issue.

    Bill

    Yes that is correct.  PACKAGE_KEEPOUT_TOP can only be defined at the board level (.brd) and it is used to prevent components from being placed in a particular area of design and in some cases a particular height.  The only exception is PACKAGE_KEEPOUT_TOP can be added to a Mechanical Symbol (.bsm).  A mechanical symbol is used to generate a master Board Outline, Keepouts and Keepin for a design which is generated the same way a package symbol (component) is generated but with a mechanical symbols you have the ability to add PACKAGE_KEEPOUT_TOP to it during creation.  Most people do not use Mechanical Symbols for their Master Board Outline symbol anymore and instead use a Master Layout (.brd) which contains the master board outline which was generated at the Layout level (.brd)

    YES I do see a benefit of having the Dynamic DFA for component clearances available during Edit Move.  I thought I heard that this functionality was coming in a future release at this past CDNLive! but I may be mistaking.

    Hope this helps,
    Michael Catrambone
    • Post Points: 20
  • Wed, Oct 8 2008 10:47 AM

    • mcatramb91
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    Re: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    Bill,

    At one point the symbol editor would not allow you to generate a package symbol with a PACKAGE_KEEPOUT_TOP shape because it was an illegal subclass for a package symbol but for some reason it is no longer doing this and allows the symbol to be created.  I don't know if it is a bug or an enhancement to the tools.

    This is sort of a loaded question which would lead to a lot of discussion but this is the place for it so here it is:

    Why would you need to add a PACKAGE_KEEPOUT_TOP to a Package Symbol when PLACE_BOUND_TOP actually does what you need?  In other words, why not expand the PLACE_BOUND_TOP to meet your clearance requirements that you are trying to meet with the addition of the PACKAGE_KEEPOUT_TOP.

    If the PACKAGE_KEEPOUT_TOP defined in the Symbol Level violates the PACKAGE_KEEPOUT_TOP at the Board Level you will never see a DRC Error which, in my opinion, you would want to see.

    Regards,
    Michael Catrambone

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  • Wed, Oct 8 2008 11:00 AM

    • pcbgeorge
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    RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply
    DFA works in Allegro 15.7, but I am not sure at what "Level" it starts working (I think XL).
    • Post Points: 20
  • Wed, Oct 8 2008 11:07 AM

    • Randy R
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    Re: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    The reason I would use a PKG KO TOP instead of expanding the Placebound is because I use the placebound to define the size of the part and this is important when I export to my mechanical team using IDF files.

    Good Day, R².
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  • Wed, Oct 8 2008 11:08 AM

    • mcatramb91
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    Re: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    Hey George,

    Yep, I am using the DFA Checks today and from what I remember it was included with Allegro Expert 610 which turned into Allegro PCB Design XL. 

    I have a question for you.  Have you seen the Dynamic DFA DRCs appear when you moving components with the Move Command?  I have only see this Dynamic DFA DRC work using Place Manual (Place > Manually..) or even better "place manual -h"

    Thanks,
    Michael Catrambone

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  • Wed, Oct 8 2008 11:23 AM

    • pcbgeorge
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    RE: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply
    Yeah, that is what I have seen, too.  A bit of a hassle, but worth it. :)
     
    I am evaluating a translation script I can run every night to translate the Valor ERFs into a global .dfa file, has anyone on the forum already done this sort of thing?
    • Post Points: 20
  • Wed, Oct 8 2008 11:33 AM

    • lcanx2
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    RE: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply
    Why would you need to add a PACKAGE_KEEPOUT_TOP to a Package Symbol when PLACE_BOUND_TOP actually does what you need?  In other words, why not expand the PLACE_BOUND_TOP to meet your clearance requirements that you are trying to meet with the addition of the PACKAGE_KEEPOUT_TOP.

    Hi Mike,

    I believe you ask a great question.  To answer your question honestly though I can’t limit my response to just the place bound top, for example:  When dealing with Press Pin components, every design site has contract Manufacturers with varying guidelines for both top and bottom clearance requirements.  These clearance requirements are not always the same although some designers may make them the same to compensate for the limits of the tool.  I believe, if we are to achieve the dense placements needed, while adhering to contract manufacturers requirements, the flexibility for individual TOP and BOTTOM accurate clearances for press pin components is essential.  As an alternative, I have experimented with using dfa_bound_bottom and assigning the appropriate fields in the spreadsheet but I am still in the test stage of this strategy.  Another example is Selective solder or when a solder pallet is used on the Wave solder side of the board.  The Side 2 clearances of SMD’s from PTH components are different on Side 1 than they are on Side 2. Furthermore, on side 2 you measure from the PTH pin to the SMD component were side 1 you are measuring body to body – So, what you are doing here is keeping out a package on side 2 of a component that is placed on side 1.

    I am in the process of hashing out what works best for our design process. I’m certainly open to other peoples ideas/experiences.

    Bill
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  • Wed, Oct 8 2008 12:29 PM

    • mcatramb91
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    Re: RE: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    Bill,

    As far as the Place_bound_top, the post from "Randy R" actually made a very good point that the Place_bound_top is used by the IDF Interface to form the component boundary / height on the Pro-E side so having it extended out to accomidate additional clearance would generate the incorrect component boundary on the Pro-E side.

    As far as the Press Fit clearance, I build them into the Package Symbol using Place_bound_top shapes using the recommended tooling from the component manufacturer and of course run this past our Contract Manufacture House to insure that it is acceptable or not.  The CM sometimes wants to save money and create their own press fit tooling but from past experience if they do not have capable folks at the CM it will lead to all types of issues.

    As far as the Selective wave clearances, I build them at the Board Level after/during placement activities mainly because I normally group these thru hole components together to share the same Selective wave window to conserve placement space.  These are generated using Package Keepouts top and bottom and YES it is very difficult when placement changes and the Keepouts don't move with the components but I would simply run out of placement space if I did not share the Selective wave keepouts so it is something that must be done at the Board Level.  I have not really found a better way of doing it but this way seems to work for me at least. 

    Normally, we only have a Selective Wave keepout on the opposite side of the thru hole component and never had a different clearance from the body of selective wave components. The selective wave clearance is from PTH Pin to SMD Component on Side 2 is the only requirement I need to meet.

    Good luck,
    Michael Catrambone

    • Post Points: 5
  • Tue, May 14 2013 10:26 AM

    • badair
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    Re: RE: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    PCBGeorge,

    Whatever became of your script evaluation?

    Bret

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  • Sun, May 19 2013 5:33 PM

    • ScottCad
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    Re: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply
    Mike I am curious about the Place bound top as there is a bit of a catch 22 with using it. Let me explain best I can. The place bound top is also used by the 3d viewer but the catch 22 is if you want to make a good 3d view of your part then you can’t really use the place bound top for full drc of the part.

    Assume for a sec we have a standard 1206 symbol with a silk screen defined around the part that has a stroke width of 10 mils. Now if you want a good 3d representation of this part then using the place bound top you would draw a rectangle that kind of sits between the pads as it would look in the real world on a board instead of drawing the rectangle to encompass the actual outline of the symbol.

    So the begging question is when creating symbols what class should one really use to define the perimeter of the component. Is the place bound top the best choice considering the issue with 3d or should I be using another class instead for component keepouts. With the release of 16.6 They have step model support now so this might mean that the Place Bound Top class is a good choice to use for the symbol to symbol spacing DRC but possibly not for relases prior to this.

    Looking in the standard libs, the place bound top of the "package class" is widely used but it is not correct if one wants a good 3d view of the part.

    Thanks All for the insight, this is a good thread

    Scott
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  • Mon, May 20 2013 8:31 AM

    • mcatramb91
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    Re: RE: RE: Place_Bound_Top vs Dfa_Bound_Top vs Package_Keepout_Top? Reply

    Hi Scott,

    Very old thread and a lot has changed since then.  Let me try to respond the best way I can.

    3D Viewer:
    With the release of the 3D viewer (3D Viewer is fairly new functionality), oversized PLACE_BOUND_TOP can make the component view in 3D very misleading, even if the PLACE_BOUND_TOP was sized the exact size of the component. Obviously this is greatly improved with the ability to map a true 3D STEP file to the components so the 3D View is very realistic.

    IDF Export to Mechanical Package:
    You do have the ability to remap a components 3D representation (3D Box) using a different Package Geometry subclass when exporting an IDF file to a mechanical package but it does not change the way the 3D viewer looks in Allegro. The variables that control this is IDF_PLACE_BOUNDS_TOP and IDF_PLACE_BOARDS_BOTTOM with a value matching the SUBCLASS name under Package Geometry.  During export it will look at these subclasses for shapes to drive the 3D Box instead of the PLACE_BOUND_TOP and PLACE_BOUND_BOTTOM but it doesn't help you with the 3D Viewer.

    Component DRC Errors:
    The PLACE_BOUND_TOP and PLACE_BOUND_BOTTOM Subclasses will generate a DRC when they come in contact with each other during placement which is one of its main purposes. You could make it smaller to just include the body of the component but you may miss a component to component DRC because of it.  Sure, you may see a Pin to Pin DRC when the pins come in contact with each other but you will not see a DRC on the PACKAGE_TOP and PACKAGE_BOTTOM subclasses.

    PACKAGE KEEPOUT defined in symbols:
    You have the ability to define a shape on PACKAGE KEEPOUT / TOP in the symbol but when these shapes come in contact with each other during placement they will never show a DRC Error.  A DRC error will only occur when a shape from PACKAGE GEOMETRY / PLACE_BOUND_TOP comes in contact with a shape on PACKAGE KEEPOUT / TOP.

    I really don't have an answer for you regarding the results in the 3D Viewer when the PLACE_BOUND_TOP is defined larger than the component but if the PLACE_BOUND_TOP does not include the pins of the device you may miss component to component DRCs during placement.  The original intent for the PLACE_BOUND shapes were to provide a simple way of generating DRCs when two component come in contact with each other.

    The other discussion in the thread was the DFA_BOUND_TOP and DFA_BOUND_BOTTOM subclasses, they are used by the real-time DFA checks that are built into Allegro. You develop a spreadsheet of component to component clearances and they will be checked to the DFA_BOUND subclasses.

    Sorry for the long response

    Hope this helps,
    Mike Catrambone

    • Post Points: 20
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Started by EE92780 at 30 Sep 2008 12:12 PM. Topic has 15 replies.