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 How to Compile System Verilog 

Last post Thu, Oct 25 2012 11:43 PM by chandanc9. 10 replies.
Started by System Verilog 19 Sep 2008 01:06 AM. Topic has 10 replies and 13343 views
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  • Fri, Sep 19 2008 1:06 AM

    How to Compile System Verilog Reply

    Hi,

    I use ncverilog: 05.70-s015: (c) Copyright 1995-2007 Cadence Design Systems, Inc.

    TOOL:   ncverilog       05.70-s015:

    and foll switches

        -update
        +access+r
        +sv31a

    I egt the foll errs

    class mem_base_object;
        |
    ncvlog: *E,EXPMPA (../models/mem_base_object.sv,3|4): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
    (`include file: ../models/mem_base_object.sv | line 3, `include file: ../models/memory_top.sv line 3, file: ../tb/memory_tb.sv line 4)

      mem_txgen txgen;
                    |
    ncvlog: *E,ILLPDL (../models/memory_top.sv,11|16): Mixing of ansi & non-ansi style port declaration is not legal.
    (`include file: ../models/memory_top.sv line 11, file: ../tb/memory_tb.sv line 4)
      mem_scoreboard sb;

    pls let me know a solution

    Thanks

    Chandra

    Force10 Networks Inc, SJC

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  • Fri, Sep 19 2008 5:20 AM

    • Shalom B
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    Re: How to Compile System Verilog Reply

    Use a newer version of NC, and use the switch +sv.

     

    Shalom

    Shalom.Bresticker@intel.com
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  • Mon, Sep 22 2008 9:00 AM

    • tpylant
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    Re: How to Compile System Verilog Reply

    The current version of NC-Verilog is IUS81-s006. Therefore, the version you are using is quite old and may be lacking some of the construct support that you require. I definitely recommend installing a later release.

    For your current issue, I'm guessing that you have your class definition outside of a module or package which be considered the "compilation unit scope". This is not supported until IUS62. Move your class definition inside of your module and see if that removes the problem for IUS57. 

    Tim

    • Post Points: 5
  • Fri, Oct 24 2008 2:56 AM

    • adua
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    Re: How to Compile System Verilog Reply

    Use irun to compile & simulate in a single step any/all hdl/hvl supported by Incisive platform.

    irun is a smart utility that can compile the file based on the default extension.

    Check the irun documentation in <ius_inst_dir>/doc/irun/irun.pdf

     rgds,

    Amit

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  • Thu, Oct 25 2012 12:27 AM

    • chandanc9
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    Re: How to Compile System Verilog Reply

    Hi All,

     I am trying to run systemverilog files using :

    irun -f filelist . 

    irun: 10.20-p008: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    TOOL: irun 10.20-p008: Started on Oct 23, 2012 at 09:54:13 IST
    irun
     -f filelist
      Globals.sv
      rtl.sv
      interface.sv
      top.sv
      Packet.sv
      Driver.sv
      Receiver.sv
      Coverage.sv
      Scoreboard.sv
      Environemnt.sv
      testcase.sv
    file: Globals.sv
    file: rtl.sv
    file: interface.sv
    file: top.sv
    file: Packet.sv
    file: Driver.sv
    file: Receiver.sv
    file: Coverage.sv
    file: Scoreboard.sv
    file: Environemnt.sv
    file: testcase.sv
      Caching library 'worklib' ....... Done
     Elaborating the design hierarchy:
     Top level design units:
      $unit_0x04bbcec2
      top
      output_intf[0].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,56|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[1].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,57|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[2].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,58|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
      output_intf[3].cb.read    <= 0;
                |
    ncelab: *E,ASNUSE (./Environemnt.sv,59|12): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.
    TOOL: irun 10.20-p008: Exiting on Oct 23, 2012 at 09:54:15 IST  (total: 00:00:02)

     

    -------------------------------------------------

    Environemnt.sv  has following:

    class Environment ;

     

    virtual mem_interface.MEM mem_intf ;

    virtual input_interface.IP input_intf ;

    virtual output_interface.OP output_intf[4] ;

     

    Driver drvr;

    Receiver rcvr[4];

    Scoreboard sb;

    mailbox drvr2sb ;

    mailbox rcvr2sb ;

    function new(virtual mem_interface.MEM mem_intf_new ,

    virtual input_interface.IP input_intf_new ,

    virtual output_interface.OP output_intf_new[4] );

    this.mem_intf = mem_intf_new ;

    this.input_intf = input_intf_new ;

    this.output_intf = output_intf_new ;

    $display(" %0d : Environemnt : created env object",$time);

    endfunction : new

    function void build();

    $display(" %0d : Environemnt : start of build() method",$time);

    drvr2sb = new();

    rcvr2sb = new();

    sb = new(drvr2sb,rcvr2sb);

    drvr= new(input_intf,drvr2sb);

    foreach(rcvr[i])

    rcvr[i]= new(output_intf[i],rcvr2sb);

    $display(" %0d : Environemnt : end of build() method",$time);

    endfunction : build

    task reset();

    $display(" %0d : Environemnt : start of reset() method",$time);

    // Drive all DUT inputs to a known state

    mem_intf.cb.mem_data <= 0;

    mem_intf.cb.mem_add <= 0;

    mem_intf.cb.mem_en <= 0;

    mem_intf.cb.mem_rd_wr <= 0;

    input_intf.cb.data_in <= 0;

    input_intf.cb.data_status <= 0;

    output_intf[0].cb.read <= 0;

    output_intf[1].cb.read <= 0;

    output_intf[2].cb.read <= 0;

    output_intf[3].cb.read <= 0;

     

    // Reset the DUT

    input_intf.reset <= 1;

    repeat (4) @ input_intf.clock;

    input_intf.reset <= 0;

     

    $display(" %0d : Environemnt : end of reset() method",$time);

    endtask : reset

     

     

     Please help me to rectify these errors

    Thanks and regards,

    Chandan

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  • Thu, Oct 25 2012 6:15 AM

    • tpylant
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    Re: How to Compile System Verilog Reply
    We need to see the interface and clocking block since that is what it is complaining about.
    Tim
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  • Thu, Oct 25 2012 7:28 AM

    • chandanc9
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    Re: How to Compile System Verilog Reply

    Thanks for your kind reply. Following is the code for output interface :

    interface output_interface(input bit clock);

      logic    [7:0] data_out;

      logic    ready;

      logic    read;

      clocking cb@(posedge clock);

        default input #1 output #1;

        input     data_out;

        input     ready;

        output    read;

      endclocking

      modport OP(clocking cb,input clock);

     

    endinterface

     ---------------------------------------

     testcase file these interfaces are passed as :

    program testcase(mem_interface.MEM mem_intf,input_interface.IP input_intf,output_interface.OP output_intf[4]);

    initial begin

    env = new(mem_intf,input_intf,output_intf);

    -------------------------------------------------------

    then as above environment class has :

     virtual mem_interface.MEM mem_intf ;

    virtual input_interface.IP input_intf ;

    virtual output_interface.OP output_intf[4] ;

    function new(virtual mem_interface.MEM mem_intf_new , virtual input_interface.IP input_intf_new , virtual output_interface.OP output_intf_new[4] ); 

    task reset();

    output_intf[0].cb.read <= 0;

    output_intf[1].cb.read <= 0;

    output_intf[2].cb.read <= 0;

    output_intf[3].cb.read <= 0;

    which shows the error 

      

     

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  • Thu, Oct 25 2012 8:52 AM

    • tpylant
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    RE: How to Compile System Verilog Reply

    Using IUS versions 10.2, 11.1, and 12.1, I had no problem in running this code:

    class Environment ;

      virtual output_interface.OP output_intf[2] ;

      

      function new( virtual output_interface.OP output_intf_new[2] );

        this.output_intf = output_intf_new ;

        $display(" %0d : Environemnt : created env object",$time);

        reset ;

      endfunction : new

     

      task reset();

        $display(" %0d : Environemnt : start of reset() method",$time);

        // Drive all DUT inputs to a known state

        output_intf[0].cb.read <= 0;

        output_intf[1].cb.read <= 0;

        $display(" %0d : Environemnt : end of reset() method",$time);

      endtask : reset

    endclass : Environment

    interface output_interface();

      logic    read;

      logic    clock;

      clocking cb@(posedge clock);

        default input #1 output #1;

        output    read;

      endclocking

      modport OP(clocking cb,input clock);

    endinterface

     

    module top;

      output_interface o[2]();

      Environment env = new(o);

    endmodule

    Do you get an error if you run this code? If not, what are you doing differently?

    Tim

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  • Thu, Oct 25 2012 10:26 PM

    • chandanc9
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    Re: RE: How to Compile System Verilog Reply

    Thanks Tim. I am still getting the same error. I ran this code (modified calling reset task from run task )

    class Environment ;

      virtual output_interface.OP output_intf[2] ;

      function new( virtual output_interface.OP output_intf_new[2] );

        this.output_intf = output_intf_new ;

        $display(" %0d : Environemnt : created env object",$time);

      endfunction : new

      task reset();

        $display(" %0d : Environemnt : start of reset() method",$time);

        // Drive all DUT inputs to a known state

        output_intf[0].cb.read <= 0;

        output_intf[1].cb.read <= 0;

        $display(" %0d : Environemnt : end of reset() method",$time);

      endtask : reset

    task run();
            reset();
    endtask : run

    endclass : Environment


    interface output_interface(input bit clock);

      logic    read;

     clocking cb@(posedge clock);

        default input #1 output #1;

        output    read;

      endclocking

      modport OP(clocking cb,input clock);

    endinterface

     

    module top;

    bit clock;

    initial
            forever #10 clock = ~clock;

      output_interface o[2](clock);

      Environment env = new(o);

    endmodule
    --------------------------------------------

    the log file reads:

    irun: 10.20-p008: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
    TOOL:   irun    10.20-p008: Started on Oct 26, 2012 at 10:58:10 IST
    irun
            tpylant.sv
    file: tpylant.sv
            interface worklib.output_interface:sv
                    errors: 0, warnings: 0
            module worklib.top:sv
                    errors: 0, warnings: 0
                    Caching library 'worklib' ....... Done
            Elaborating the design hierarchy:
            Top level design units:
                    $unit_0x7631bed7
                    top
        output_intf[0].cb.read <= 0;
                  |
    ncelab: *E,ASNUSE (./tpylant.sv,21|14): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
        output_intf[1].cb.read <= 0;
                  |
    ncelab: *E,ASNUSE (./tpylant.sv,23|14): Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
    irun: *E,ELBERR: Error during elaboration (status 1), exiting.
    TOOL:   irun    10.20-p008: Exiting on Oct 26, 2012 at 10:58:11 IST  (total: 00:00:01)

    Is this problem due to tool version ?

    Regards,

    Chandan

     

     

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  • Thu, Oct 25 2012 10:38 PM

    • Shalom B
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    Re: RE: How to Compile System Verilog Reply

    I don't have 10.20-p008, but this exact example runs for me in 10.20-s009.

     

    Shalom

    Shalom.Bresticker@intel.com
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  • Thu, Oct 25 2012 11:43 PM

    • chandanc9
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    Re: RE: How to Compile System Verilog Reply

    Thanks Shalom. Then it seems to be version problem. If anyone could please point to alternative

    -Chandan

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Started by System Verilog at 19 Sep 2008 01:06 AM. Topic has 10 replies.