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 Register Classes for SystemVerilog OVM 

Last post Tue, Sep 9 2008 6:20 PM by AnilRaj. 0 replies.
Started by AnilRaj 09 Sep 2008 06:20 PM. Topic has 0 replies and 11304 views
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  • Tue, Sep 9 2008 6:20 PM

    • AnilRaj
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    • Joined on Tue, Sep 9 2008
    • Posts 1
    • Points 5
    Register Classes for SystemVerilog OVM Reply

    Hi, I am uploading a register class, which can be used for modeling hardware registers. I am uploading the source code and examples on how to run it. I also have a user guide which has all the APIs listed and explained. The user guide is ARV.pdf in the attached tar file. I have named the class ARV, which stands for Architect's Register View. It has got very good randomization and coverage features. Users have told me that its better than RAL. You can download it from http://verisilica.info/ARV.php
    . There is a limit of 750KB in this cadence website. The ARV file is 4MB. That is why, I am uploading it at this site. I have a big pdf documentation and a doxygen documentation there. That is the reason for the bigger file size. The password to open the ZIP file is ovm_arv. I hope, everyone will use these classes.

    Please contact me for any help.
    Regards ANil

    • Post Points: 5
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Started by AnilRaj at 09 Sep 2008 06:20 PM. Topic has 0 replies.