I would like to specify to RtlCompiler that some pin ([enable] pin of tristate cells) on combinationnal cells must be considered as sync pin.
The goal is to stop timing path at the input pin of tristate, and balance timing with clock on enable pin.
Without that, tristate are condiderered as clock gating cells and the path are extended after theses cells.
Now, the only solution i found, is to perform synthesis with timing violation (more run time, and area...) and to specify clocktree in encounter with the Cts specfile, i would like to have a timing clean design at synthesis step.
Thanks, if you have solution.