Home > Community > Forums > IC Packaging and SiP Design > Of interest: "Chips-in-a-SiP” are a circuit simulation headache"

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Of interest: "Chips-in-a-SiP” are a circuit simulation headache" 

Last post Tue, Aug 12 2008 11:54 AM by Dieds. 0 replies.
Started by Dieds 12 Aug 2008 11:54 AM. Topic has 0 replies and 3649 views
Page 1 of 1 (1 items)
Sort Posts:
  • Tue, Aug 12 2008 11:54 AM

    • Dieds
    • Top 500 Contributor
    • Joined on Fri, Jun 13 2008
    • San Jose, CA
    • Posts 28
    • Points 695
    Of interest: "Chips-in-a-SiP” are a circuit simulation headache" Reply
    Of interest to folks in this forum: In the latest “Chip Design” magazine, there is an article titled: “‘Chips-in-a-SiP’” are a circuit simulation headache” 


    Inked by Cadence’s Taranjit Kukal and Keith Felton, the authors describe how today's chip-level circuit simulation environment needs to be able to attach IC package technology to the chip design. Have a read and share your thoughts below.

     

    Cadence community manager
    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by Dieds at 12 Aug 2008 11:54 AM. Topic has 0 replies.