One subtle implication of lowering the operating voltage of a power domain in a design that employs voltage scaling is: the more you lower the operating voltage, the worse timing becomes (cells have less drive strength, more delay etc). Therefore, in order to get back to the original timing, the synthesis tool has to optimize the design further. This *might* lead to the designer not getting as much power savings as originally expected.
Therefore, it's helpful to be using a library set that is less sensitive to operating voltages (timing-wise), when applying voltage scaling to a design.
Originally posted in cdnusers.org by wtan