Cadence Community

How to change the solder mask of pads from top to bottom in brd file

Varun1610 — Fri, 14 Jun 2013 06:35:34 GMT

I placed the components on top layer and mirrored. Components have been placed in the bottom layer but some how the solder mask layer of the component pins is displaying as solder mask top.

It should change to solder mask bottom. Let me know some remedy for this, as I am facing this problem in many instances.

VIA SELECTION

Nayyierwajih — Wed, 19 Jun 2013 10:59:51 GMT

Hi all

Is there any way by which we can select any specific via in the PCB editor.

For e.g if there are about 10 types of vias in any pcb design and there is a via having name "60rd40" and i have to make the subdrawing of only one type of via for e.g "60rd40" then what should be the procedure?

Regards

Nayyier

Orcad PCB EDITOR 16.6 FOOTPRINT LIBRARY

RobZan — Fri, 14 Jun 2013 12:54:59 GMT

Hi @all!

I would like to know if is possible to download the footprint library ( file *.dra and *.psm) of the most popular component.

I can not manually create each footprint!!! The standard footprint in \SPB_16.6\share\pcb\pcb_lib\symbols are not enough.

Can someone help me???

Thank's

Spectre mixsignal simulation error

tangyaoyun — Thu, 20 Jun 2013 07:04:12 GMT

Hi everyone :

I have done a mixsignal simulation by AMS, but when I finished all settings and click "netlist and run". It stopped at CIW and showed the following message

"errors encountered during simulation. the simulator run log has not been generated. Possible cause could be an invalid command line option for the version of the simulator you are running. choose setup ->environment and verify that the command line option specified in the userCmdLineOption field are supported for the simulator. Alternatively run the simulator standalone using the runSimulation file in the netlist directory to know the exact cause of the error." What is wrong with it, any people could tell me the root course, thank you?

Ruler removed with undo command in IC6

Sridhar123 — Thu, 20 Jun 2013 06:48:31 GMT

Hello all,

We recently moved from IC 5 version to IC6 . I see that in this version ruler is being removed upon using the undo command where as this not the case in IC5 , is there a way to avoid this.

Best regards,

Sri.

Place by Schematic page...

C Shiva — Tue, 18 Jun 2013 06:46:40 GMT

Hi All,

In one of our new design, due to large number of parts, we would like to place the parts as "Place by schematic page number". But in our tool the option is disabled. If anyone knows how to enable it, kindly help us.

Attached a screen shot for reference. Using Allegro PCB design L v16.01

Thanks,

Shiva.

List operation

Pawandeep — Thu, 20 Jun 2013 04:51:28 GMT

Hi,

I would like to know the difference in between these two statements

'(1 2)

list(1 2)

I tried to run the attached listOp.il file and it showed some unexpected behavior for me.

Thanks,

Pawan

Asynchronous FIFO design

abhinavpr — Tue, 18 Jun 2013 10:56:35 GMT

Hi,

I am new to logic design and trying to design an Asynchronous FIFO. can somebody suggest some good docs to read?

regards,

abhinavpr

Triggering callbacks on specific devices

navi2582 — Thu, 20 Jun 2013 01:42:18 GMT

Hi,

I am using "CCSinvokeCdfCallbacks.il" and "CCSCdfCallbackEntireLib.il" skill procedures to trigger callbacks on a entire library, running with the following options,

-->CCSinvokeCdfCallbacks(cv ?callInitProc t ?useInstCDF t ?order list("l" "w"))

With this, the callback functions are applied to all the devices (mos, res, dio etc.,) in all the cells in the library. Is there a way to apply to callback just for MOS specific devices only and not for RES or DIO devices?

Thanks,

how to compare designware like DW02_multp with LEC

codefire — Sun, 28 Sep 2008 03:48:24 GMT

hi everyone,

Our design instantced a lot designware and we always compare these designware with their behavior model when run FV with LEC. This method always works, only except DW02_multp and some other designware. So, we'll blackbox these designware to pass the FV. But as DC do a lot of optimization to DW02_multp's input and output pins, while we must set constraints accordingly. These constraints lead to so many troubles to us as our design changes or re-synthesize. I was wondering if there is any way we also can compare DW02_multp without any blackboxes set. Thanks!