Cadence Community

Multi dimensional array

sprinter — Fri, 20 Nov 2009 23:40:08 GMT

Hi,

How can I create multi dimensional array in order to name variables like:

cp_6_4

cp_5_3

cp_4_2

.cp_m_m-2

etc.

Thanks,

Adil.

Encounter v7.1 warnings and errors

AMS 2003 — Fri, 20 Nov 2009 21:55:09 GMT

Hi all,

There are a number of warnings when I try to load a design into Encounter. I am a first-time user and totally confused.

1) **WARN: There is no overlap layer defined in any lef file so you are unable to create rectilinear partition in a hierarchical flow.

2) **ERROR: No MANUFACTURINGGRID value was given. It is set to minimum LEF unit of 0.005 um. If this value is not right, a MANUFACTURINGGRID statement must be added in the technology lef file.

I went through a post about manufacturing grid on this community to change the lef file.

everybody uses 0.005, but then DATABASE 1000 was in their LEF file. Its 2000 in mine, What can I do about this?

3) **WARN: The cell has already been defined in another LEF file, or earlier in this LEF file. All data except the antenna data will be ignored. If the data in both cell definitions is needed, manually merge the data into one definition.

4) **WARN: TLF library 'slow' is version 4.1. Only versions 4.3 or higher are supported. You are forcing the reader to continue with this TLF library. Due to many differences in threshold handling, library units, and sequential cell models, the results in timing analysis, technology mapping, test synthesis and power analysis may be incorrect. It is strongly recommended that a new TLF library with version 4.3 or higher be obtained. If this TLF was translated from Synopsys library (.lib), the latest syn2tlf tool can be used to generate new TLF automatically.

-- to solve this I generated the updated tlf file using syn2tlf tool. and changed my .conf file accordingly, but it still gave me the warning. May be it is still sourcing the old file.

5) No function defined for cell 'power pad'. The cell will only be used for analysis

6) **WARN: No lower reported slew threshold for rising transition specified, assuming default value of 10%

From all these warnings and errors, I think there is a problem with my LEF file basically. What could I do to upgrade that? May be contact the technology provider for an upgraded version?

Thanks in advance.

Clocking blocks /cycle based sampling and driving

hipooja — Wed, 04 Nov 2009 09:44:46 GMT

Hi,

I read that clocking block / cycle based simulation in SV promotes reusability.Why is that so? I understand that interface definition simplifies the signal connection How does this promote reusability?

Regards,

Pooja Vaishnav.

Einstein's puzzle (System Verilog) solved by Incisive92

Vinayhonnavara — Fri, 20 Nov 2009 20:54:07 GMT

Hello All,

Following is the einstein's puzzle solved by cadence Incisive92 (solved in less than 3 seconds -> FAST!!!!!!)

Thanks,

Vinay Honnavara

Verification engineer at Keyu Tech

vinayh@keyutech.com

// Author: Vinay Honnavara

// Einstein formulated this problem : he said that only 2% in the world can solve this problem
// There are 5 different parameters each with 5 different attributes
// The following is the problem

// -> In a street there are five houses, painted five different colors (RED, GREEN, BLUE, YELLOW, WHITE)

// -> In each house lives a person of different nationality (GERMAN, NORWEGIAN, SWEDEN, DANISH, BRITAIN)

// -> These five homeowners each drink a different kind of beverage (TEA, WATER, MILK, COFFEE, BEER),

// -> smoke different brand of cigar (DUNHILL, PRINCE, BLUE MASTER, BLENDS, PALL MALL)

// -> and keep a different pet (BIRD, CATS, DOGS, FISH, HORSES)

///////////////////////////////////////////////////////////////////////////////////////
// *************** Einstein's riddle is: Who owns the fish? ***************************
///////////////////////////////////////////////////////////////////////////////////////

/*
Necessary clues:

1. The British man lives in a red house.
2. The Swedish man keeps dogs as pets.
3. The Danish man drinks tea.
4. The Green house is next to, and on the left of the White house.
5. The owner of the Green house drinks coffee.
6. The person who smokes Pall Mall rears birds.
7. The owner of the Yellow house smokes Dunhill.
8. The man living in the center house drinks milk.
9. The Norwegian lives in the first house.
10. The man who smokes Blends lives next to the one who keeps cats.
11. The man who keeps horses lives next to the man who smokes Dunhill.
12. The man who smokes Blue Master drinks beer.
13. The German smokes Prince.
14. The Norwegian lives next to the blue house.
15. The Blends smoker lives next to the one who drinks water.
*/

typedef enum bit [2:0] {red, green, blue, yellow, white} house_color_type;
typedef enum bit [2:0] {german, norwegian, brit, dane, swede} nationality_type;
typedef enum bit [2:0] {coffee, milk, water, beer, tea} beverage_type;
typedef enum bit [2:0] {dunhill, prince, blue_master, blends, pall_mall} cigar_type;
typedef enum bit [2:0] {birds, cats, fish, dogs, horses} pet_type;

class Einstein_problem;

   rand house_color_type house_color[5];
   rand nationality_type nationality[5];
   rand beverage_type beverage[5];
   rand cigar_type cigar[5];
   rand pet_type pet[5];
        rand int arr[5];

   constraint einstein_riddle_solver {



       foreach (house_color[i])
           foreach (house_color[j])
               if (i != j)
               house_color[i] != house_color[j];
       foreach (nationality[i])
           foreach (nationality[j])
               if (i != j)
               nationality[i] != nationality[j];
       foreach (beverage[i])
           foreach (beverage[j])
               if (i != j)
               beverage[i] != beverage[j];
       foreach (cigar[i])
           foreach (cigar[j])
               if (i != j)
               cigar[i] != cigar[j];
       foreach (pet[i])
           foreach (pet[j])
               if (i != j)
               pet[i] != pet[j];


       //1) The British man lives in a red house.
       foreach(nationality[i])
               (nationality[i] == brit) -> (house_color[i] == red);


       //2) The Swedish man keeps dogs as pets.
       foreach(nationality[i])
               (nationality[i] == swede) -> (pet[i] == dogs);


       //3) The Danish man drinks tea.
       foreach(nationality[i])
               (nationality[i] == dane) -> (beverage[i] == tea);


       //4) The Green house is next to, and on the left of the White house.
       foreach(house_color[i])
               if (i<4)
                   (house_color[i] == green) -> (house_color[i+1] == white);


       //5) The owner of the Green house drinks coffee.
       foreach(house_color[i])
               (house_color[i] == green) -> (beverage[i] == coffee);


       //6) The person who smokes Pall Mall rears birds.
       foreach(cigar[i])
               (cigar[i] == pall_mall) -> (pet[i] == birds);


       //7) The owner of the Yellow house smokes Dunhill.
       foreach(house_color[i])
               (house_color[i] == yellow) -> (cigar[i] == dunhill);


       //8) The man living in the center house drinks milk.
       foreach(house_color[i])
               if (i==2) // i==2 implies the center house (0,1,2,3,4) 2 is the center
                   beverage[i] == milk;



       //9) The Norwegian lives in the first house.
       foreach(nationality[i])
               if (i==0) // i==0 is the first house
                   nationality[i] == norwegian;



       //10) The man who smokes Blends lives next to the one who keeps cats.
       foreach(cigar[i])
               if (i==0) // if the man who smokes blends lives in the first house then the person with cats will be in the second
                   (cigar[i] == blends) -> (pet[i+1] == cats);

       foreach(cigar[i])
               if (i>0 && i<4) // if the man is not at the ends he can be on either side
                   (cigar[i] == blends) -> (pet[i-1] == cats) || (pet[i+1] == cats);

       foreach(cigar[i])
               if (i==4) // if the man is at the last
                   (cigar[i] == blends) -> (pet[i-1] == cats);

       foreach(cigar[i])
               if (i==4)
                   (pet[i] == cats) -> (cigar[i-1] == blends);


       //11) The man who keeps horses lives next to the man who smokes Dunhill.
       foreach(pet[i])
               if (i==0) // similar to the last case
                   (pet[i] == horses) -> (cigar[i+1] == dunhill);

       foreach(pet[i])
               if (i>0 & i<4)
                   (pet[i] == horses) -> (cigar[i-1] == dunhill) || (cigar[i+1] == dunhill);

       foreach(pet[i])
               if (i==4)
                   (pet[i] == horses) -> (cigar[i-1] == dunhill);


       //12) The man who smokes Blue Master drinks beer.
       foreach(cigar[i])
               (cigar[i] == blue_master) -> (beverage[i] == beer);


       //13) The German smokes Prince.
       foreach(nationality[i])
               (nationality[i] == german) -> (cigar[i] == prince);


       //14) The Norwegian lives next to the blue house.
       foreach(nationality[i])
               if (i==0)
                   (nationality[i] == norwegian) -> (house_color[i+1] == blue);

       foreach(nationality[i])
               if (i>0 & i<4)
                   (nationality[i] == norwegian) -> (house_color[i-1] == blue) || (house_color[i+1] == blue);

       foreach(nationality[i])
               if (i==4)
                   (nationality[i] == norwegian) -> (house_color[i-1] == blue);


       //15) The Blends smoker lives next to the one who drinks water.
       foreach(cigar[i])
               if (i==0)
                   (cigar[i] == blends) -> (beverage[i+1] == water);

       foreach(cigar[i])
               if (i>0 & i<4)
                   (cigar[i] == blends) -> (beverage[i-1] == water) || (beverage[i+1] == water);

       foreach(cigar[i])
               if (i==4)
                   (cigar[i] == blends) -> (beverage[i-1] == water);

   } // end of the constraint block


   // display all the attributes
   task display ;
       foreach (house_color[i])
           begin
               $display("HOUSE : %s",house_color[i].name());
           end
       foreach (nationality[i])
           begin
               $display("NATIONALITY : %s",nationality[i].name());
           end
       foreach (beverage[i])
           begin
               $display("BEVERAGE : %s",beverage[i].name());
           end
       foreach (cigar[i])
           begin
               $display("CIGAR: %s",cigar[i].name());
           end
       foreach (pet[i])
           begin
               $display("PET : %s",pet[i].name());
           end
       foreach (pet[i])
           if (pet[i] == fish)
               $display("THE ANSWER TO THE RIDDLE : The %s has %s ", nationality[i].name(), pet[i].name());

   endtask // end display


endclass

program main ;

   initial
       begin
           Einstein_problem ep;
           ep = new();
           if(!ep.randomize())
               $display("ERROR");
           ep.display();
       end
endprogram // end of main

Cannot Uninstall OrCAD 16.2 Demo Version

cccarmen — Mon, 16 Nov 2009 14:27:09 GMT

Hi all! I have recently installed OrCAD 16.2 Demo but it kept on saying there were errors during installation. Therefore, I would like to uninstall it and re-install again. But then I found out that there were not any uninstallation shortcuts / exe in the directory. So, what should I do to remove the whole programme?? Many thanks!

SV: Coverage of assertions (only count hits??)

rossbthompson — Fri, 20 Nov 2009 20:37:13 GMT

I was under the impression that assertions would be included in functional coverage. It seems that I am only get the evaluated assertions, not ones that have not fired. Is it possible to include the un-evaluated assertions as coverage holes?

I have multiple instances of the same checker (sv module), but I see different totals under the assertion column. I am new to SV, so it could be something basic.

Below is an example of what I see, all of the lines are instances of the same checker. The issue is that the assertion total is different

Coverage of immediate sub-instances:
Total    Assertion    CoverGroup Weighted    CoverGroup Bins    Name
80%    100% (5/5)    60% (1)    47% (8/17)    dbxxt_dgl
73%    100% (6/6)    46% (1)    29% (5/17)    dbxxxd_det
73%    100% (6/6)    46% (1)    29% (5/17)    dbxxxt_det
73%    100% (5/5)    46% (1)    29% (5/17)    dixxrm_det
73%    100% (6/6)    46% (1)    29% (5/17)    dbxxc_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxxp_det
80%    100% (4/4)    60% (1)    47% (8/17)    dxxxxg_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxx_det
73%    100% (5/5)    46% (1)    29% (5/17)    dxxxxin_det
73%    100% (5/5)    46% (1)    29% (5/17)    dxxxxxwv_det
73%    100% (6/6)    46% (1)    29% (5/17)    dxxxxg_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxv_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxx_det
73%    100% (4/4)    46% (1)    29% (5/17)    dxxxxt_det
73%    100% (6/6)    46% (1)    29% (5/17)    dixxxctive_det
63%    100% (2/2)    26% (1)    18% (3/17)    dxxxtive_det
78%    100% (6/6)    56% (1)    41% (7/17)    dxxxtive_det
78%    100% (6/6)    56% (1)    41% (7/17)    dxxxxxactive_det

Command:

report_html -output cov_web -all fd -inst xxx.xxxx.*

version 08.20-s015

Reg Timing Report

Music — Fri, 20 Nov 2009 20:34:27 GMT

Hi..

when i tried to check my timing report it says No constrained timing paths with given description found. Design may not be constrained or library is missing timing information.

So how do i get rid of this,,,,

and moreover my design has a clock defined in my code.

i also generated .sdc from rtl compiler by saying write_sdc > file.sdc

But this is not accurate. I would like to know the correct way to get all my setup, hold , clk delays included in mydesign.

Background color ot text when doing edit

mred — Fri, 20 Nov 2009 17:46:28 GMT

When editing text the back ground color is black. While I have the design background as black I can not see the text line on screen when in edit. This must be a simple setting I have not found it.

methods for variable integer to string conversion

JMCaJHU — Wed, 07 Oct 2009 23:21:21 GMT

Is there any way to convert a variable of the integer type to a string. Currently i must create a set of pins with names varying from IN0 onward. I tried everything from casting the int to string with quotations to evaluating the symbol/variable then casting into a string with symbolToString. All seem to be limited with no direct way from int to string. Currently i have resorted to using random naming for the program to work as follows:

for(j 0 n

if(j==0 then
db_outnet=dbCreateNet(db_outcell "IN0")
db_figId = dbCreateRect(db_outcell list("METAL1") list(0:5.025 0.375:5.4))
dbCreatePin(db_outnet db_figId "IN0")

else
outname=symbolToString(gensym('IN))
db_outnet=dbCreateNet(db_outcell outname)
db_figId = dbCreateRect(db_outcell list("METAL1") list(0:(3.7+rth*j) 0.375:(rth*j+4.1)))
dbCreatePin(db_outnet db_figId outname)

outname=symbolToString(gensym('IN))
db_outnet=dbCreateNet(db_outcell outname)
db_figId = dbCreateRect(db_outcell list("METAL1") list(0:(5.025+rth*j) 0.375:(rth*j+5.4)))
dbCreatePin(db_outnet db_figId outname)

This creates IN0 then continues creating input pins in numerical order from a random index. I need to be able to create "IN" + j.string in java terms.

unique and priority in SV

hipooja — Wed, 04 Nov 2009 08:36:51 GMT

I wanted to check if my understanding on the usage of unique and priority keywords is correct or not.Unique i understand is a keyword used to tell the synthesis tool to infer a simple mux.The statements would be evaluated in parallel and which ever becomes true ,is executed.The advantage of using 'unique' keyword is that it gives warning messages when the conditions are not mutually exclusive,and hence would be best suited for applications such as processing a read and write request to memory ,read and write requests must not overlap,incase they do ,it should be reported as an error.

Priority keyword is to inform the synthesis tool ,to infer a priority mux.This may be used to implement a priority arbitration mechanism.

Conditions are evaluated in priority.

Examples of the usage of these keywords used in TB which you have worked on will be appreciated.

Regards,

Pooja

Autoroute nets that have propagation delay and relative propagation delay

Neha Anu — Thu, 19 Nov 2009 12:11:57 GMT

Hi all,

I've to autoroute nets (A1,A2..A8) that are matchgrouped (MG1) with pin pair longest pin pair and with propagation delay .

How can I autoroute the above nets using the do file in the Specctra autorouter using the command Route->Route Editor??

Can anyone plsss xplain wats the do file command for the above scenario??

Thanx

Neha.

Cadence IC 6.1.3 licensing issues

AnalogGR — Fri, 20 Nov 2009 09:50:38 GMT

Hi,

In the CIW window says that the ' License was checked out successfully' but then when I am trying to open either a schematic or symbol or layout view ,says that cant find license

Please advice

Regards

Nik

Thermals positive planes, negative planes I'm confused

stellar — Thu, 19 Nov 2009 17:47:58 GMT

In Layout planes were always negative. I'd like to use positive planes on the present board but I don't see any connectivity on the artwork where there should be. I've defined my via as a 10mil drill with 30mil regular pad. For thermal relief I have a flash symbol defined for inner layers and my antipad is 50mil. When I set the layers to negative I see the thermals correctly. for positive planes do I need to define the inner thermal relief as a pad instead of a flash? Also if I can succeed in learning how to use positive planes I'd like no thermals on vias at all just flooded. I don't like the missing spokes and don't think thermals are necessary on vias.

Garbage collection problem

spark — Thu, 04 Jun 2009 07:24:38 GMT

Hi all,

I encounter a problem during the simulation. If the simulation time is very long then "Doing garbage collection" message always appear, the simulation will not continue smoothly. I dont know where is problem. Do I need set some specman configure to avoid this problem?

The environment is NC-SIM (IUS) 8.1 and Specman(SPMN) 8.1.

Syntax of the relative propagation delay using do file

Neha Anu — Wed, 18 Nov 2009 06:42:01 GMT

Hi all,

I'm routing the brd file using the command Route->Route Editor by using the .do files.I want to route some nets for eg: (P0,P2,P3..P7)having relatively same propagation delay.Can Anyone pls reply how to make do file syntax for this relative propagation delay??

Thanx

Neha

Customer Support Solution 11014718

stump1019 — Thu, 19 Nov 2009 19:24:06 GMT

First of all let me say that this shouldn't be this difficult to find. I've never had to do this before and I've been looking for almost a half hour trying to find this article. Anyone have any idea where I might find Allegro Design Entry HDL Customer Solution 11014718? Thanks, Mike.

Edit and Show reference designator/pin numbers in Cadence Design Entry

EdwardHU — Mon, 16 Nov 2009 20:40:59 GMT

In the transition to use Cadence PCB tools. Have used Altium/PCAD a lot in my previous careers.

Unfamiliar with the way that Cadence tool processes. After I add a component to the schematics entry tool (concept), why I don't see the reference designator and the pin numbers of the component? I tried all menu and have not found a way to do it.

Regards,

Ed

Does anyone have the 0.18um standard cell library?

learnlearn1 — Thu, 19 Nov 2009 19:14:08 GMT

Hi I want FSA0A_C 0.18 um ASIC standard cell library for synthesis. Could email me the library file if anyone has it?

Many thanks!

status of selected nets for routing

stellar — Thu, 19 Nov 2009 16:26:36 GMT

In Layout you could see the route completion status of selected nets at a glance. So far I can't figure out a way to see the same in Editor. The unconnected pin report considers all the nets in the design as does the Display/status. There must be a report that shows the status of the selected nets.

skill commands

AnalogGR — Thu, 19 Nov 2009 12:37:38 GMT

Hi I would like to swipe few commands in order to load Cadence

1. include /PDK/CRN65LP/cds.lib

2. setenv CDS_Netlisting_Mode "Analog"

Do I have to swipe them into the CIW window or in the linux terminal?

Thanks

Nik

Issues with OrCAD 16.2 demo version

David Lay at Q — Thu, 06 Aug 2009 19:22:09 GMT

The demo version is not just crippled, it's broken.

1. after skipping the license configuration a message says "Failed to get CDS_LIC_FILE value from registry. Self registration of executables might fail."

2. then you get "The OrCAD installation did not complete successfully" with instructions to run a command line.

3. then just when you thought everything was working (despite many warning messages) when you try to run a PSpice simulation you cannot intialize a profile. This of course is a complete show-stopper.

We have licences for use on campus but we want students to be able to use the demo at home. Help!

David

Queen's University at Kingston.

A question about autocontact feature ?

IC Layout — Thu, 19 Nov 2009 03:25:58 GMT

Hi! All, I am using IC514 version of cadence...

I have a question about autocontact feature in layout editor...

I have two sets of vias in my PDK...

ex:- M2_M1c, DFM_M2_M1 .... lly for all vias

By default for paths M2 and M3 (or M2 and M1) it is droping via which has "c" at the end...

i.e for M2 & M1 intersection ==> M2_M1c

M3 & M2 intersection ==> M3_M2c

Will it possible to drop my desired vias by setting any environment variable or by any means..

(I have read the post about auto contact dropping .. its fine ... but I would like to know this if possible ...)

Thnaks in Advance...

Prabhakar. K -- Layout Engineer

missing vias in stacked power rings

MMode — Thu, 19 Nov 2009 13:30:56 GMT

Hi all,

we are working in a 5 metal layer process with Encounter 5.2. In our design, we have decided to stack the power rings, i.e. the VSS ring is on metal layer 1 and the VDD ring is in the same position but on metal layer 5. However, we are confronted with the following problem during power routing: If the ring's width is greater or equal to 1001 µm (drawing dimensions), the vias from metal 3 to 4 and metal 4 to 5 are missing, so the core rows are not connected to VDD.

However, if the ring is only 1000 µm wide (or less), this problem does not occur. Unfortunately, 1000 µm is by far not enough for our design.

Another interesting thing is that the power stripes (on metal 2) are connected correctly even when their width is greater than 1000 µm. From this we draw the conclusion that this is not a problem related to viarule definitions in our LEF technology files.

Has anybody encountered a similar problem or, even better, can provide us with an explanation of this behaviour?

Thanks in advance!

How to dump DRC shape coordinates into a file?

LostInRTN — Fri, 16 Oct 2009 18:55:02 GMT

I need to get the coordinates of the polygons, rectangles, etc that are highlighted after a DRC run in the Error Layer Window. Equivalently these are the shapes the errorLayer procedure uses. I've tried geGetSelSet, the marker functions and the Hilight functions and none of these seem to be the method the ELW uses to show the DRC errors.

Thanks

Text properties in PVS ?

Selef — Thu, 19 Nov 2009 09:01:05 GMT

Hi to ALL,

does everybody know if and how we can use text properties on a DEVICE definition in a PVS (LVS) rule file.

For example in Assura this is made by extractDevice(......textProperty(..))

and in Calibre (SVRF format) by DEVICE....TEXT PROPERTY LAYER

During PVS LVS run there is a translation of SVRF format rules to PVS (masco format), but the run fails because of the TEXT PROPERTY LAYER command exist on SVRF format with user defined device error.

It seems that computational Build-In language of Calibre SVRF format (using text properties) is not translated properly to PVS (masco) format.

Is it something equivalent to the above statements in PVS (masco format) ?

Thanks,

Stavros