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Custom IC Design Forum

Page 4 of 160     First 12345678 ... Last
  Topics   Replies     Views     Last Post  
Post small signal TF from a file as a gain element in schematic.
started by vamshiky  on 01 Aug 2014 02:42 AM   
1 453 By Andrew Beckett
04 Aug 2014 06:19 AM   
Post Making a monte carlo simulation component specific
started by simbamford  on 25 Feb 2013 02:36 AM   
7 1472 By Andrew Beckett
01 Aug 2014 06:11 AM   
Post How can you create a global net in a Spectre netlist that does not end in !
started by Bret Howe  on 31 Jul 2014 03:02 PM   
5 464 By Andrew Beckett
01 Aug 2014 01:38 AM   
Post From spectremdl to ultrasim : any cadence solution ?
started by samung  on 24 Jul 2014 08:03 AM   
7 468 By samung
31 Jul 2014 09:11 AM   
Post Generating ocean script in Linux terminal.
started by RFStuff  on 30 Jun 2014 11:28 PM   
3 773 By skillUser
30 Jul 2014 10:34 AM   
Post parametric analysis of mosfet length and width
started by madhanmo  on 30 Jul 2014 09:49 AM   
0 468 By madhanmo
30 Jul 2014 09:49 AM   
Post Memory instance : ULTRASIM simulator setting
started by samung  on 30 Jul 2014 07:07 AM   
0 446 By samung
30 Jul 2014 07:07 AM   
Post ADEXL parametric sweep does not work
started by sram8t  on 10 Jul 2014 04:59 AM   
1 503 By Andrew Beckett
30 Jul 2014 02:47 AM   
Post Extracted parameters do not match with the schematic.
started by jagadishdn  on 15 Jul 2014 10:34 PM   
2 396 By jagadishdn
29 Jul 2014 10:01 PM   
Post How to multiply a waveform with the x axis vector
started by milind0y  on 25 Jul 2014 01:39 PM   
2 438 By milind0y
29 Jul 2014 10:52 AM   
Post Layout Porting between Foundries
started by KKANDOTH  on 23 Jul 2014 06:54 AM   
5 423 By theopaone
29 Jul 2014 10:05 AM   
Post Link pin labels over hierarchy
started by Narasimhan90  on 28 Jul 2014 11:15 AM   
3 422 By Andrew Beckett
29 Jul 2014 09:59 AM   
Post Knowing associated TECH-FILE location
started by RFStuff  on 14 Jul 2014 01:59 PM   
3 434 By Andrew Beckett
29 Jul 2014 07:32 AM   
Post Entering infoname and info (captab) analysis in ADE
started by RFStuff  on 29 Jul 2014 02:53 AM   
3 429 By Andrew Beckett
29 Jul 2014 04:04 AM   
Post Processing cadence result data from psf folder
started by RFStuff  on 11 Jul 2014 06:01 AM   
7 536 By Andrew Beckett
29 Jul 2014 02:49 AM   
Post NC-Verilog netlister setttings to output single netlist (not hierarchy-ihnl/ based)
started by jagarcia85  on 09 Apr 2011 03:45 AM   
3 1699 By Andrew Beckett
29 Jul 2014 02:35 AM   
Post Zoom-in and Zoom-out graphics issues in Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151)
started by RFStuff  on 27 Jun 2014 10:28 AM   
1 843 By Andrew Beckett
29 Jul 2014 01:50 AM   
Post Annoying message about OS compatibility and SKILL IDE problem
started by Kovinko  on 21 Jul 2014 02:02 PM   
2 408 By Andrew Beckett
29 Jul 2014 01:07 AM   
Post CDS_THRU ISSUE- "umc/tsmc"
started by KarthikJaiho  on 18 Jun 2014 11:37 PM   
1 1095 By Quek
28 Jul 2014 10:21 PM   
Post Import Files for Encounter ( Preparing for Encounter)
started by Mr Aseem  on 20 Jun 2014 01:04 PM   
1 1436 By Quek
28 Jul 2014 10:15 PM   

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