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Logic Design Forum

Page 1 of 28     12345 ... Last
  Topics   Replies     Views     Last Post  
Sticky Logic Design Forum Posting Guidelines
started by tstark  on 06 Feb 2014 11:02 AM   
0 5426 By tstark
06 Feb 2014 11:02 AM   
Post RC response[TUI-39]after "report clock_gating"
started by cwwang  on Today at 07:49 AM   
0 15 By cwwang
Today at 07:49 AM   
Post Using multiple libraries - mixed elaboration flow
started by drovak  on 23 Sep 2014 09:01 AM   
0 285 By drovak
23 Sep 2014 09:01 AM   
Post Mining information from RTL Compiler log file.
started by sgauria  on 22 Sep 2014 08:14 AM   
0 274 By sgauria
22 Sep 2014 08:14 AM   
Post Using RC to estimate leakage & dynamic power from different synthesis runs
started by kenearth  on 28 Aug 2014 11:00 AM   
0 1401 By kenearth
28 Aug 2014 11:00 AM   
Post How to perform dynamic power analysis using RTL compiler
started by marten  on 18 Aug 2014 08:19 AM   
1 1564 By grasshopper
18 Aug 2014 08:44 AM   
Post LEC debug points report generation ???
started by aperla  on 29 May 2014 08:03 AM   
2 3316 By sogold
22 Jul 2014 07:53 PM   
Post LEC - Conformal RTL to netlist mismatch
started by hnfq  on 11 Jul 2012 12:21 PM   
11 8024 By grasshopper
08 Jul 2014 06:53 AM   
Post what is the Purpose of initial_target attribute of a cost group?
started by anudeep  on 23 May 2014 11:43 AM   
0 3139 By anudeep
23 May 2014 11:43 AM   
Post LEC mismatch b/w RTL and Lec-Friendly netlist
started by anudeep  on 23 May 2014 11:36 AM   
0 3140 By anudeep
23 May 2014 11:36 AM   
Post how to synthesize delay elements in RTL complier
started by micro469  on 17 Apr 2014 11:25 AM   
3 3319 By grasshopper
24 Apr 2014 07:23 PM   
Post unmapped points with Conformal
started by nozuey  on 24 Apr 2014 04:59 PM   
0 3174 By nozuey
24 Apr 2014 04:59 PM   
Post How to force a small gate structure during RTL Compiler synthesis?
started by rexnyu  on 24 Apr 2014 11:09 AM   
0 3177 By rexnyu
24 Apr 2014 11:09 AM   
Post Avoid race condition at SPI_slave synthesis
started by alphus  on 21 Apr 2014 03:03 AM   
0 3149 By alphus
21 Apr 2014 03:03 AM   
Post Unsupported SDC Commands(remove_attribute) in RC
started by doydodo  on 21 Apr 2014 12:37 AM   
0 3130 By doydodo
21 Apr 2014 12:37 AM   
Post How to simulate after synthesis in NC launch or NC sim
started by micro469  on 17 Apr 2014 11:37 AM   
1 3208 By grasshopper
17 Apr 2014 08:24 PM   
Post conformal LEC
started by Indira S  on 13 Apr 2014 11:28 PM   
0 3008 By Indira S
13 Apr 2014 11:28 PM   
Post clock gating in RC
started by doydodo  on 09 Apr 2014 11:33 PM   
1 3002 By bmiller
10 Apr 2014 08:37 AM   
Post Conformal ECO - Equivalanece check
started by Prashant M  on 09 Apr 2014 04:52 AM   
0 3090 By Prashant M
09 Apr 2014 04:52 AM   
Post How to set ignore for some of blackbox pins in LEC?
started by lc337199  on 01 Apr 2014 04:40 PM   
1 3160 By lc337199
04 Apr 2014 03:31 PM   

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