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Whiteboard Wednesdays - Closing the Memory Wall Gap

Comments(2)Filed under: UFS, EMMC, 3D Memory, HBM, DDR4, Tensilica, Memory, Design IP, Wide I/O, DDR4 3DS, HMC, 2D Memory

We're excited to introduce Whiteboard Wednesdays, a new video blog series that will shed some light and provide some practical insights on how to address a variety of intellectual property (IP-) related design challenges. Our inaugural segment addresses the memory wall gap--that phenomenon that occurs when the bandwidth of microprocessors outpaces the bandwidth of the memory in the design, degrading system performance. 

Watch our first Whiteboard Wednesdays episode, where Cadence's Scott Jacobson takes a closer look at how CPU performance outstrips memory transfers and the options available to system designers. He also covers 2D solutions like EMMC 5.0, UFS, and DDR4, as well as 3D solutions like HMC, HBM, Wide I/O2, and DDR4 3DS.

We hope you find this series to be helpful. We also welcome your feedback. Share your ideas for future episodes and any other comments or questions in the Comments area under this blog post.  


By Gary Delp on February 3, 2014
It is a nice start, and clearly buzzword compliant - you got many of the issues out on the table.  I look forward to some projections on how far the gap can be closed and what kind of modeling Cadence (Denali + Tensilica +++)  supports.  This is a hot topic across the industry, so I expect that you will need to deep dives to keep your audience. Thanks for starting the series.  Are there e-mail reminders to sign up for?

By scottj05 on February 11, 2014
Gary, thanks for the feedback.  Indeed this is a very hot topic in the memory industry today and we are developing further Whiteboard Wednesday sessions to delve deeper into this topic.  Stay tuned...

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