The Power of Cadence System Power Flow vs. Viewing from the Top

I think you are a bi ...

Anonymous — Sat, 15 Nov 2008 21:28:55 GMT

I think you are a bit pessimistic about virtual platforms.... if they are derivatives of current designs and created a sufficiently high level of abstraction, they can be created in a matter of days or weeks rather than months or years. A six-to-twelve-month span sounds like a pretty detailed clock-level model, which is not what you should start with. Go for software-timed or loosely-timed, as discussed by Jason Andrews at Cadence some time ago: www.cadence.com/.../is-host-code-execution-history.aspx

In the end, you need both. A VP to get software started early and ideas for whether a design is useful at all, and then hardware acceleration to check the final design against your detailed goals.

A longer discussion is at jakob.engbloms.se/.../344

In many cases the "m ...

Anonymous — Fri, 07 Nov 2008 03:59:19 GMT

In many cases the "missing model syndrome" is what holds back virtual platforms. Even a fairly comprehensive TLM IP library doesn't cover the custom hardware being designed. It's hard to justify spending a lot of time to create models for the virtual platform when hardware engineers are busy creating RTL, software engineers are busy writing software, and verification engineers are busy finding bugs in both. Some companies are investing the time, but not enough. Emulation has been successful for many years because it uses "design artifacts" that everybody must create, RTL. As C-to-Silicon spreads it will make SystemC models available as design artifacts, not as a separate project just to enable software execution. Making virtual platforms easier to create in a shorter time with better linkage to the design process is critical. There will always be pros and cons of virtual models vs. actual models (emulation and FPGA prototypes), both play a vital role and both are needed as a foundation for tasks such as verification and power analysis.

Hi Ran: Thanks for y ...

Anonymous — Wed, 05 Nov 2008 18:54:04 GMT

Hi Ran: Thanks for your post. it looks like we agree on a couple of things, especially that power analysis as early as possible is very important. The flow Cadence suggests works pretty well and I have seen it at users being used. One remaining issue is how well the synthesized results correlate to the actual implementation later. Please find more detail in my post at www.synopsysoc.org/viewfromtop. Our means are different but no solution is universal ...