System Design and Verification - All Comments

Amarkant, Yes, y ...

jasona — Wed, 11 Jan 2012 16:40:53 GMT

Amarkant,

Yes, you can install Ubuntu without VirtualBox, this is only an option for those people who can't or don't want to re-partition the disk or are forced to use Windows.

Another option I used before is Wubi, the Ubuntu Windows Installer www.ubuntu.com/.../windows-installer

Jason

I already have ubunt ...

Anonymous — Wed, 11 Jan 2012 16:31:53 GMT

I already have ubuntu 11.10 in different partition . is it necessary to use Virtual box again for installation of ubuntu 11.10 .

Can I install Cadence directly in ubuntu 11.10 without virtual box ?

please help...

Thanking You ,

Amarkant Kumar

Interesting blog pos ...

Anonymous — Mon, 09 Jan 2012 19:59:57 GMT

Interesting blog post! Typical story - hardware devices tend to accept pretty much any access thrown at it without anything bad happening at runtime. While a virtual platform written from specs and manuals pretty much is guaranteed to flag these. And flag them you should, since you never know if a bad access is a documented workaround, a poorly documented register, a defined location that does nothing but is explicitly reserved for future expansion - or an actual error in the driver that will bite you some time later.

I wrote a piece of this last year too, at blogs.windriver.com/.../being-helpful-or-simply-correct.html

The TLM or the class ...

Anonymous — Sat, 07 Jan 2012 12:35:46 GMT

The TLM or the class based verification methedology is not so amazing. I am working on porting the older verilog test bench to new UVM test bench. Now I need to worry about the complexities of object/class communication as well as the design. So the work is more challenging and takes more time. I need to wait and watch if it is really worth.

May be starting the environment from the scratch will be more rewarding??

Your article is real ...

Anonymous — Wed, 04 Jan 2012 09:05:03 GMT

Your article is really informative and it seems that now its time to move towards SystemC and TLM. And now we also have CtoS kind of simulators as well.

One problem that I h ...

Anonymous — Tue, 03 Jan 2012 12:49:05 GMT

One problem that I had faced when running Zynq virtual box on my laptop was that my laptop bios was not configured for vt-x/AMD-V property. So when I started virtual box I got an error message. After some digging into Google search I found that virtual box needs vt-x/AMD-V enabled in the BIOS of host computer. Once I enabled things flew past smoothly.

Excellent article, a ...

Anonymous — Wed, 21 Dec 2011 18:07:03 GMT

Excellent article, and I concur with the sentiments. SystemC needs to be debugged with a SystemC aware debugger. [NOTE: TLM is now part of SystemC as of IEEE-1666-2011]

Nice post !, the inf ...

Anonymous — Tue, 22 Nov 2011 09:46:54 GMT

Nice post !, the information shared is truly helpful and yes software development will definitely cause industrial revolution in today's world.

An extrapolation on ...

Anonymous — Fri, 18 Nov 2011 17:43:27 GMT

An extrapolation on the example in this article:

An assembly line is manufacturing cars. It takes eight hours to manufacture a car and that the factory produces one hundred and twenty cars per day.

The latency is: 8 hours.

The throughput is: 120 cars / day or 5 cars / hour.

----

What if I build another identical assembly line to manufacture more cars? It still takes eight hours to manufacture a care on this new assembly line, however now I have two lines with twice as many employees, so my throughput is doubled.

The latency is: 8 hours.

The throughput is: 120 cars / line / day or 10 cars / hour.

This example shows that doubling the assembly line facilities (hardware) and doubling the number of employees (software) results in doubling the throughput.

----

What if I can reduce the speed of both assembly lines by 50% and use the employees from the first assembly line to work both lines?

It would now take 12 hours to manufacture each car and each line would produce 80 cars per day.

The latency is: 12 hours.

The throughput is: 80 cars / line / day or 6.67 cars / hour.

This example shows that doubling the assembly line facilities (hardware) but keeping the number of employees (software) constant, results in increased throughput, even though the latency is higher.

Jason, I guess yo ...

Anonymous — Fri, 18 Nov 2011 07:27:02 GMT

Jason,

I guess you found the command line options "-DISTCOMP" and "-DISTCOMPJOBS nr" to support parallel compilation. I don't see why this won't work on a single machine?

greetz,

Bas

Blog Review: Oct. 14 | System-Level Design

Blog Review: Oct. 14 | System-Level Design — Fri, 04 Nov 2011 18:57:17 GMT

Pingback from Blog Review: Oct. 14 | System-Level Design

Great post, that sa ...

Anonymous — Fri, 28 Oct 2011 16:00:50 GMT

Great post, that saved me last night when it would have been too late to call support!

Thank you very much ...

Anonymous — Wed, 07 Sep 2011 13:15:00 GMT

Thank you very much for the nice article Jason!

The team has now released a new revision of this document. Adding Cortex-A15, Large Physical Address Extension (LPAE) and also a new chapter on virtualization...

Feedback received from readers was also integrated :)

Kind regards,

Alban Rampon

ARM Connected Community

Hi Jason, Nice de ...

Anonymous — Fri, 19 Aug 2011 07:31:05 GMT

Hi Jason,

Nice description and glad you found the Embecosm article useful.

We've recently been simulating Ethernet using TUN/TAP, allowing you to connect to models via FTP/telnet as though they are on a real network. I haven't written it up yet, but that is very relevant to your next article.

Best wishes,

Jeremy Bennett

Tel: +44 (1590) 610184

Cell: +44 (7970) 676050

SkypeID: jeremybennett

Email: jeremy.bennett@embecosm.com

Web: www.embecosm.com

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Does cadence support ...

Anonymous — Tue, 26 Jul 2011 02:27:53 GMT

Does cadence support emulation of a multiple FPGA chip design? i.e. Virtex (1-4 types)

Also there tool(s) that support algorithm (inittially developed in MATLAB, later coded in VHDL) partitioning into multiple FPGAs?

Thank you,

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Useful and practical ...

Anonymous — Tue, 14 Jun 2011 23:38:05 GMT

Useful and practical !!!

Thank you very much :-)

The term “software d ...

Anonymous — Thu, 26 May 2011 11:30:09 GMT

The term “software development” may be used to refer to the activity of computer programming, which is the process of writing and maintaining the source code, but in a broader sense of the term it includes all that is involved between the conception of the desired software through to the final manifestation of the software, ideally in a planned and structured process.

Alina @ foutsventures

Software development ...

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Mike and Steve: exc ...

Anonymous — Tue, 24 May 2011 20:52:09 GMT

Mike and Steve: excellent webinar and presentation.

Can you provide more detailed information regarding the interconnect design between the CPU and the external controller used in the initiator driven device?

What about an existing Verilog design that is being ported to a device similar to Android platform. Looks like already working Verilog code would need to be recoded into System-C prior to even getting the testing environment to work.

If you have strange ...

Anonymous — Wed, 18 May 2011 04:34:42 GMT

If you have strange fonts in simvision try this:

$ sudo apt-get install ttf-mscorefonts-installer

I just learned, that ...

Anonymous — Wed, 27 Apr 2011 14:06:07 GMT

I just learned, that to use gcc 4.4, which comes with INCISIV on ubuntu 10.10 or 10.04 you have to remove or rename the following files:

IUS_INSTALL_DIR/tools/systemc/gcc/4.4-x86_64/install/lib/gcc/x86_64-redhat-linux/4.4.0/include-fixed/features.h

IUS_INSTALL_DIR/tools/systemc/gcc/4.4/install/lib/gcc/i686-pc-linux-gnu/4.4.0/include-fixed/features.h

Otherwise I ran into weird errors complaining about 'uselocale'.

Now I can even run SystemC designs on Ubuntu!

Jason, Nice colu ...

LarryL — Wed, 13 Apr 2011 23:01:21 GMT

Jason,

Nice column, and thanks for the link to the Open Virtual Platforms (OVP) website.

The thing is, if you showed Gary's diagram to someone, and asked them which of the three areas they were talking about, as often as not in our experience, the answer is "Yes". They are interested in all three. Then we start asking about priorities, and specific issues that need solving in the different areas, and still no resolution is achieved.

There is still a significant effort needed, not so much on what the models are, or the uses of those models, but on how best to implement various methodologies that take advantage of those different virtual platforms. And that is going to have to be a collaborative effort between tool developers and users.

Larry

I don't think System ...

Anonymous — Wed, 13 Apr 2011 13:25:58 GMT

I don't think SystemC is a mess, I personally just believe that SystemC lacks a clear/defined/shared methodology which makes its usage quite difficult to new comers ... and more than this the incredible lack of Modeling Engineers (SW guys with HW/System sensibility) is a really important issue to be rapidly solved to make ESL a success ...

I hate RHEL.. so be ...

Anonymous — Thu, 07 Apr 2011 23:30:20 GMT

I hate RHEL.. so behind. So It was nice to bring up an ubuntu box in my office. Initially it was just a terminal nice way to serve vnc sessions... and I had to ssh into the old boxes to run IUS. But now I have the tools local. Much faster.

I should note that I still have to fall back on the RHEL4 boxes when I get weird ubuntu behaviour... but it's still nice to have.

Thanks!

Some updates:

In ubuntu 10.10 64-bit I had to install the 32bit libs to get installscape to run:

sudo apt-get install ia32-libs

And for the lmtools I needed lsb:

sudo apt-get install lsb

I also had to make the changes you mentioned -- installing ksh and csh and adding soft links for sh, basename and sort.

I installed java too - when I was trying to figure out the library issue, but it turns out that it was probably unnecessary.

SystemC should be pr ...

rradhakr — Tue, 15 Mar 2011 17:30:48 GMT

SystemC should be primarily used for modeling algorithms at a high level of abstraction. The primary reason for moving to a higher level of abstraction is simulation speed. You don't want to verify functionality at the RT-level. Do not fall into the trap of thinking at the RTL level of abstraction for SystemC.

There reason that algorithm designers/architects in chip companies do not use Verilog --its too low level.

Abstraction level makes a much larger impact on simulation speed than language. C++ is significantly easier and more compact for writing high abstraction than Verilog. SystemC adds to the wide usage of C++ by adding hardware-specific concepts and more importantly, concurrency/parallelism capabilities. SystemC's data types offer a lot of operations (concat, range,etc) for coding flexibility.

Once you have a valid SystemC model, you can use High-Level Synthesis (HLS) to generate a RTL model. One of the benefits of HLS is that it allows the architect/designer to model the designs functionality without any concern for microarchitectural implementation details --like what happens in any specific clock cycle. As you get more experience coding SystemC for HLS, you will see the huge benefits of the code being easier to write, read and debug, plus it simulates so much faster. Let the HLS tool, like the Cadence C-to-Silicon Compiler do all the hard work of generating low-level RTL Verilog for the rest of your design flow.

Well. I am well into ...

manrajgujral — Mon, 14 Mar 2011 15:11:50 GMT

Well. I am well into my next semester now, and here’s the thing

1. Moving from VHDL to Verilog was a relief.

2. Moving from Verilog to System Verilog was again a huge improvement. Though it wasn’t a big change, but one felt Sys. Verilog was a natural evolution of Verilog.

3. Sys. Verilog to SystemC seems like a step back. It is like going back in time.

Reasons:

Sys. Verilog has these concurrent events which can be modelled so easily. Simple logic for e.g.:

(a) For a wire/logic definition for signals is so neat. Compare it to sysC where you need to first define the mode "sc_in" , then define the type "sc_bool" ...define the size, if any, then define the signal name.

(b) Rising edge and falling edge can only be done for signals defined as "sc_clk" is seems. (Maybe there are options that i haven’t heard)

(c)where is the concatenate command in SysC? It is so easy to manipulate arrays and bits in Sys Verilog by using simple "{}" that the designer doesn’t have to bother doing the right-shits and then ORing...or any basic level coding - which could easily result in more coding time and error prone too.

Well, I have just listed random things from the top of my head. These are the first impressions to Sys C, and maybe I am too naive in this area, but as a beginner - that’s my feedback. It feels like a step back.

How can I build a pr ...

Anonymous — Fri, 11 Mar 2011 22:20:13 GMT

How can I build a precompiled model? I've tried "irun -compile -f file'" and to use that model: "irun -libmap lib.map -top cfg". I've defined the cds.lib and hdl.var files too. But I have some errors. Is that ok? Must use -compile ?

Thanks!!

SystemC is a mess fo ...

Anonymous — Fri, 04 Mar 2011 03:25:15 GMT

SystemC is a mess for the hardware engineers mostly. In my 3+ years experience with SystemC, the main challenge was the C++ nature of the platform for the RTL developers.

There are multiple attempts from the EDA vendors to help bridge the gap by creating UML to SystemC translators. Another huge challenge of modeling in general is to show positive ROI at the beginning of the process. Next in line is the challenge of obtaining and sharing the models, but this is semi-successfully solved by TLM2.

FPGA prototyping sys ...

Ran Avinun — Mon, 28 Feb 2011 00:46:16 GMT

FPGA prototyping systems are very important and are complementary to emulation systems. They are being used mostly when the design is matured and the numbers of iterations is small. The main use model for FPGA prototyping is software development and exhaustive regressions with focus on emulation replicates running at high performance. Emulation is being used earlier in the design phase mostly for system validation with focus on HW and SW debug and advanced verification acceleration as an expansion to RTL and TLM (SW-based) simulation. With all the debug options available, FPGA prototyping systems are still limited in their debug capability, bring-up time and turnaround time compared to emulation. As I mentioned, in 2010, we have seen a growing demand for emulation. The same companies that demanded higher emulation capacity are also using FPGA prototyping and fully aware to the benefits and drawbacks of these systems. Still, they chose to increase their emulation footprint. In the forceable future, I can see both emulation and FPGA prototyping systems demand and capacity growing.

SystemC is a mess. ...

Anonymous — Thu, 24 Feb 2011 18:32:47 GMT

SystemC is a mess. It uses bad abstractions/semantics on top of a shared-memory paradigm that makes it difficult to parallel process and a threading model that stops it modeling things in detail. So it's not good for software engineers or low-level hardware verification (gates,power management/analog/RF).

Here's a better approach -

http://parallel.cc

- compatible with SystemC, but with much broader reach. Open source so anyone can use it.

Gene,Thanks for ...

Anonymous — Wed, 23 Feb 2011 22:54:06 GMT

Gene,

Thanks for commenting. There are many instances of inferior technology gaining widespread adoption because of standardization and interoperability. My observation is that many companies are not interested to adopt stand-alone tools or languages that are not based on open standards, are not available from multiple vendors, and don't connect to anything else they do in the system design process (even if there are warts).

This means it would be very hard to replace SystemC, even if you have something better.

Jason

* SystemC has comple ...

Anonymous — Wed, 23 Feb 2011 20:20:05 GMT

* SystemC has complex classes built with C++

That's because SystemC is not well designed. A good design makes complex things simple, a bad design makes simple things complex.

* It uses strange macros like SC_MODULE, SC_METHOD, and SC_HAS_PROCESS

These also demonstrate the design problems with SystemC. There is absolutely no need in those ugly macros, and no surprise here that GBL has none of those.

With FPGA prototypin ...

Anonymous — Tue, 22 Feb 2011 04:46:58 GMT

With FPGA prototyping systems taking 10-20 million gate designs and very good debug options available like TotalHistory, Protolink, Inpa etc, will it not be sunset for the million dollar emulator systems ?

SystemC is neither c ...

Anonymous — Wed, 26 Jan 2011 13:06:28 GMT

SystemC is neither convoluted nor outdated. I am concerned that you would push your own relatively new products in this area. I note that your products are only supported on Windows. The GBL library does not appear to be available separately without the tools, which require licensing.It is unclear if it is truly open-source or what body of engineers has reviewed it. Your credentials are decent.

No, it's not complic ...

Anonymous — Tue, 25 Jan 2011 18:39:37 GMT

No, it's not complicated, just convoluted and very much outdated. Naturally, for beginners and experts alike I recommend GBL library instead of SystemC.

I am a student at th ...

manrajgujral — Mon, 24 Jan 2011 18:31:29 GMT

I am a student at the moment, moving from Verilog/Sys. Verilog to systemC next semester.

As of now, I am confident to model a system from an ASM chart to Verilog/Sys Verilog. And, to be honest, it took a while to get hang of the sequential and combinational parts.

I hope SystemC is how you've put it. (i've had C/C++ before too). Looking forward to it

Hey Jason. Great a ...

Anonymous — Wed, 12 Jan 2011 11:08:13 GMT

Hey Jason.

Great article. (actually great series :-)

I ve been wondering how do you link the simvision memory viewer to the program.

Is it statically using a snapshot of the memory or do you dynamically link to qemu ?

Patrick

Also check out http: ...

Anonymous — Wed, 08 Dec 2010 03:27:39 GMT

Also check out http://elinux.org

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There's news from In ...

Anonymous — Fri, 05 Nov 2010 14:57:36 GMT

There's news from Intel about Yocto:

www.thinq.co.uk/.../yocto-project-rolled-out

Maybe you should als ...

Anonymous — Sat, 30 Oct 2010 04:12:45 GMT

Maybe you should also check out the Yocto Project. It was just launched this week, so I can understand if you have not heard of it. It's a Linux Foundation project. http://www.yoctoproject.org

Jason, As someone l ...

Anonymous — Fri, 29 Oct 2010 05:59:47 GMT

Jason,

As someone living in "The Rest of The State" Minnesota, Android is definitely big, even here. For the countless other consumer devices out there running embedded Linux, this is the first one consumers know and ask for by name.

You have a pretty good list going. For anyone interested in learning more about the workings of Linux, I suggest just downloading the kernel sources and looking through the many READMEs/docs included with it, or even portions of the source that are well documented.

Another interesting site, although not specific to embedded Linux, is the Linux Weather Forecast at www.linuxfoundation.org/.../lwf

wow that's kind of i ...

Anonymous — Thu, 21 Oct 2010 18:30:01 GMT

wow that's kind of insulting. I seen more systems "engineers" who fail to grasp the difference than h/w "designers".

Hi! Jason, How can ...

Anonymous — Wed, 29 Sep 2010 05:41:03 GMT

Hi! Jason,

How can i add DWARF debugging information into my current C code. Is it like at the time of Declaration/Definition of Variable I should add these DWARF type in my code or my compiler will automatically add these information in my c-code.

Regards,

Mohit

Very interesting!

vuong — Thu, 26 Aug 2010 16:18:30 GMT

Very interesting!

Hi there, I had the ...

Anonymous — Wed, 25 Aug 2010 12:37:58 GMT

Hi there,

I had the same problems as Pablo did.

I managed to run the hello program correctly using:

$sudo qemu-arm-static hello

In order to correct map the program I used the option:" -T your_codesourcery_install/arm-none-eabi/lib/generic-hosted.ld" as jasona suggested.