System Design and Verification

Android System Verification Part 2

jasona — Fri, 13 Nov 2009 14:00:00 GMT

In Part 1 of this series on Android System Verification I provided the basics about how to run the Android emulator. When I initially looked at the emulator I was looking for information about available verification techniques, primarily at the system...(read more)

We and Our Competitors Agree (Well, Almost!)

SteveSvoboda — Thu, 12 Nov 2009 14:00:00 GMT

It’s rare in EDA to see competitors agreeing, but an interesting article in EEtimes Europe this week caught my eye, by Lauro Rizzatti the VP Mktg of EVE. Lauro discussed a survey EVE ran during DAC, where they asked customers how they felt about...(read more)

Android System Verification Part 1

jasona — Mon, 09 Nov 2009 14:00:00 GMT

From time to time I hear or read stories about how engineers find ways to apply Specman to verification problems that are outside of normal RTL verification. Often times they are about connecting Specman to a post-silicon environment such as a physical...(read more)

Emulation Is Here To Stay

Ran Avinun — Tue, 03 Nov 2009 00:29:00 GMT

A recent blog by Brian Bailey covered the emulation war. I would like to correct some of the facts Brian has mentioned and also add my own comments. First, Brian, you owe Cadence an apology :) You forgot some of the emulation announcements from Cadence...(read more)

From Cadence Earning Call This Week

Ran Avinun — Mon, 02 Nov 2009 19:01:00 GMT

In system development, we have focused on two key customer challenges. First, we are increasing their productivity by elevating design and verification to the next level of abstraction. This quarter, we announced the industry’s first transaction...(read more)

Improve Productivity Through Communication and Learning

jasona — Mon, 02 Nov 2009 15:00:00 GMT

I regularly spend time talking to people about the importance of the connection between embedded software and hardware design and verification. If you have been following my writing on cadence.com you know that it takes more than tools to succeed on a...(read more)

4G Is Here Now

Ran Avinun — Tue, 27 Oct 2009 13:00:00 GMT

If you have not heard about 4G yet, it is here now. Verizon has already paid earlier this year $9.4B for an open access to the new spectrum. It'll be using the spectrum as the core of their high-speed 4G LTE network - see below. http://gizmodo.com...(read more)

Keeping Trident Missiles "On Target" With System-Level Verification

SteveSvoboda — Fri, 23 Oct 2009 22:00:00 GMT

Can you think of a more critical application for system-level verification than making ABSOLUTELY CERTAIN a missile carrying nearly 5 Megatons of nuclear payload doesn't have any "bugs"? We've all seen enough James Bond and Superman...(read more)

Synopsys’ “Synphony” Announcement – Welcome to the Party!

SteveSvoboda — Wed, 14 Oct 2009 21:39:00 GMT

I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge productivity...(read more)

Webcast: EDA, ESL and More Ideas From DAC

jasona — Tue, 13 Oct 2009 14:41:00 GMT

From the events calendar, OpenSystems Media is hosting a webcast tomorrow titled EDA, ESL, and More Ideas from DAC that will be hosted by Don Dingee and feature presentations and discussion from Frank Schirrmeister from Synopsys, Shabtay Matalon from...(read more)

Virtualization and Simulation Roundtable

jasona — Tue, 13 Oct 2009 14:03:00 GMT

A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com . Please have a look if you are interested in Virtual Platform usage for embedded software. One of the things that...(read more)

Intrusive Software Debugging: Friend or Foe?

jasona — Tue, 06 Oct 2009 13:00:00 GMT

One of the great benefits of working with simulation (RTL, SystemC , or any Virtual Platform) is the ability to provide non-intrusive interactive software debugging. Interactive software debugging provides the control and data access needed to inspect...(read more)

Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

SteveSvoboda — Sun, 04 Oct 2009 00:39:00 GMT

Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009 . With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attendance than back...(read more)

Must Have Advanced Verification to Achieve Software Signoff

Steve Brown — Thu, 24 Sep 2009 13:00:00 GMT

In a recent blog on EDA Graffiti , Paul McClellan he talks about Software Signoff. He loosely defines it as high level synthesis of C/C++ describing the system, with some of the code built into an FPGA and the rest remains application software. He identifies...(read more)

What's the New CMO Mean For Cadence and System Design and Verification?

Steve Brown — Tue, 22 Sep 2009 16:10:00 GMT

If you track Cadence stock or other EDA leadership news you undoubtedly know we've hired John Bruggeman as our new Chief Marketing Officer (CMO) and Vice President of Marketing. He's been part of some very dynamic companies, and most recently...(read more)