System Design and Verification

The Zynq Virtual Platform: Not Just for Pre-Silicon

jasona — Wed, 08 Feb 2012 04:29:00 GMT

One of the biggest misconceptions about Virtual Platforms is that they are only useful for pre-silicon software development, and once a chip and board is ready they are quickly discarded. Even after boards are available, Virtual Platforms are valuable...(read more)

System-Level Design and the Waves of EDA

fschirrmeister — Mon, 30 Jan 2012 17:00:00 GMT

Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago. 2011 was an interesting year for system...(read more)

Creating the Zynq Virtual Platform, Including Errata

jasona — Fri, 06 Jan 2012 17:00:00 GMT

Although I have never contributed any code to the Linux kernel, the headline We are all Linux developers now on linux today caught my eye. One of the things that amazes me is how many embedded products use Linux and how they deal with all of the complexity...(read more)

Ubuntu Updates for 2012

jasona — Mon, 02 Jan 2012 17:00:00 GMT

I'm overdue to provide an update on how to run Virtual System Platform (VSP) and Incisive on the latest version of Ubuntu . My last article was very helpful to many people and users provided additional insight about what worked for them. Just before...(read more)

TLM: The Year in Review, and Trends for 2012

Jack Erickson — Mon, 02 Jan 2012 14:00:00 GMT

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally...(read more)

One Oil Change and Update my Car to the Latest Software Patch, Please!

fschirrmeister — Tue, 20 Dec 2011 19:00:00 GMT

Since the IEEE Spectrum article "This Car Runs on Code" back in February 2009, my interest in the requirements for software and system-level development in automotive applications has grown quite a bit. And after recently having reviewed in...(read more)

High Level Synthesis for a Control-Dominated Design?

Jack Erickson — Thu, 15 Dec 2011 18:18:00 GMT

CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences...(read more)

Equine Anatomy, Pax Romana and the Reach of Standards

fschirrmeister — Wed, 14 Dec 2011 14:00:00 GMT

At the recent Synopsys EDA Interoperability Forum, the opening session focused on a 10 year review of standards and interoperability between EDA tools. Three speakers -- Philippe Magarshack (Central R&D Group VP, STMicroelectronics), John Goodenough...(read more)

How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

Jack Erickson — Tue, 22 Nov 2011 14:00:00 GMT

During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately...(read more)

Will Software Development Cause Another “Industrial” Revolution?

fschirrmeister — Mon, 21 Nov 2011 17:15:00 GMT

As you have read here before, Cadence has been working closely with Xilinx to create an extensible virtual prototype for the Zynq extensible platform . I have previously written about the need and value for extending virtual platforms at the transaction...(read more)

Parallel Compilation for SystemC

jasona — Thu, 17 Nov 2011 16:00:00 GMT

One of the most common complaints about SystemC is that it takes too long to compile. I tend to agree that it does take longer to compile compared to C or Verilog. The primary reason is that SystemC is a somewhat complex set of libraries built on top...(read more)

Welcome to the Zynq-7000 Virtual Platform

jasona — Fri, 28 Oct 2011 15:10:00 GMT

As you might guess we are pretty excited about the Virtual Platform development for the Zynq-7000 EPP . The FPGA world has changed a lot from 1995 when I was an FAE at Cypress Semiconductor selling and supporting programmable logic devices. This was during...(read more)

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

jasona — Mon, 24 Oct 2011 13:00:00 GMT

This is the last installment of my series on different uses for the UART in Virtual Platforms. Today's article is about how to use a UART as a way to capture logging information about a running system. One of the challenges of developing embedded...(read more)

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?

Jack Erickson — Tue, 04 Oct 2011 15:00:00 GMT

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm. Two thoughts...(read more)

edaForum: Evolving Devices from “All in One” to “One for All”

fschirrmeister — Mon, 26 Sep 2011 19:00:00 GMT

This week I had the pleasure to attend and to present at the 11 th annual edaForum , held in Berlin, Germany. Coming back to my hometown and presenting at this conference was a real treat, even though the traffic was much worse than I remembered, mostly...(read more)

Virtual Platform UART Use Number 3: Using gdb to Debug a Software Application

jasona — Thu, 22 Sep 2011 15:00:00 GMT

This is the next installment in my series covering the uses of the venerable UART in Virtual Platform simulation. Use the links below to review the previous articles: Introduction Connecting an xterm to a UART Using telnet to connect to a UART This article...(read more)

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

jasona — Tue, 06 Sep 2011 15:00:00 GMT

Welcome to the next installment in my series about different ways to use the venerable UART in Virtual Platforms. If you missed the first two parts you can review the introduction and use case 1, about using xterm in slave mode for an interactive terminal...(read more)

Virtual Platform UART Use Number 1: Connecting to an Interactive Terminal

jasona — Thu, 18 Aug 2011 15:00:00 GMT

Welcome to the first example of using a UART in a Virtual Platform. For those just joining, I outlined a list of four UART uses in my previous introduction . One of the most common ways to use a UART in a Virtual Platform is to connect to a terminal and...(read more)

IP Cannot be an Efficient Abstraction Level Without SystemC!

Jack Erickson — Fri, 12 Aug 2011 18:00:00 GMT

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that...(read more)

Virtual Flash Memory Gets Real

Steve Brown — Mon, 08 Aug 2011 23:00:00 GMT

This week's Flash Memory summit will not only highlight the IP Cadence delivers, but will touch on innovative application of virtual prototype technology for Flash Memory firmware and system development. Developing complex memory controllers is challenging...(read more)

A Must Read: the ARM Cortex-A Programmer's Guide

jasona — Thu, 04 Aug 2011 20:00:00 GMT

For the last couple of years, I have been getting a lot of e-mail from different LinkedIn groups. I'm interested in groups like Android, Embedded Linux, ARM, EDA Bloggers, and more. A majority of the days I don't have time to read much (or any...(read more)

Four Uses for the Venerable Virtual Platform UART

jasona — Wed, 27 Jul 2011 17:00:00 GMT

The Universal Asynchronous Receiver/Transmitter (UART) is one of the oldest hardware peripherals, and yet it is is still present in many embedded systems created today. I'm not sure when it was invented, but Wikipedia says it was designed by Gordon...(read more)

ARM Generic Interrupt Controller HOWTO

jasona — Fri, 22 Jul 2011 15:00:00 GMT

Way back in 2004, I wrote a book called Co-Verification of Hardware and Software for ARM SoC Design . At that time the world revolved around AHB and the ARM926EJ-S was a popular CPU. All ARM CPUs used two interrupt signals, nIRQ and nFIQ . The nIRQ signal...(read more)

Creating SystemC TLM-2.0 Peripheral Models

TeamESL — Thu, 14 Jul 2011 18:00:00 GMT

Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than time...(read more)

A SystemC Virtual Platform Overflowing the Stack -- Just Before DAC

jasona — Tue, 14 Jun 2011 16:00:00 GMT

Thanks to all who stopped by the Cadence booth to see and talk about the Cadence Virtual System Platform at DAC . I spent most of the week in meetings and giving presentations and demos so I don't have any insight into the virtual platform related...(read more)

Using the ARM Profiler with the Cadence Virtual System Platform

jasona — Mon, 13 Jun 2011 16:00:00 GMT

I have posted a new article over at blogs.arm.com covering the current integration of the ARM Profiler with the Cadence Virtual System Platform . It's a must read for users interested in profiling software running on a virtual platform. If you have...(read more)

Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!

Steve Brown — Mon, 23 May 2011 16:00:00 GMT

It's been an exciting month for the System Realization team with the announcement of our System Development Suite . One of the new products, the Cadence Virtual System Platform , made its debut at the Embedded Systems Conference and has generated...(read more)

Blazing a Trail With Ubuntu

jasona — Mon, 23 May 2011 13:00:00 GMT

One of the most popular blogs I wrote is running Incisive on Ubuntu . I have had a number of questions and comments, as well as thanks for pointing out some of details on how to make everything work. One person even had the suggestion to start a user...(read more)

Panel Discussion: Applying High-Level Synthesis in an SoC Flow

Jack Erickson — Mon, 16 May 2011 17:00:00 GMT

Last Thursday, EETimes hosted a virtual System on Chip event focused on IP integration in SoCs. Even with IP re-use comprising a large percentage of new SoCs, new IP must also be developed in order to differentiate on the hardware side. With RTL containing...(read more)

System Development Suite - Connecting Software to Hardware Design and Verification

Jack Erickson — Mon, 09 May 2011 13:00:00 GMT

I've been at CDNLive! EMEA watching demos of the newly announced System Development suite, and it's mindblowing. I'm seeing good old ncsim running Android interactively on the Virtual System Platform. You open an app in the virtual Android...(read more)

Yes We Can...Do FPGA-Based Prototoyping

Juergen57 — Fri, 06 May 2011 13:00:00 GMT

As part of this week's System Development Suite announcement , Cadence introduced two new platforms, the Virtual System Platform and the Rapid Prototyping Platform. Both new platforms help users start embedded software development much earlier, thus...(read more)

Welcome to the Cadence Virtual System Platform

jasona — Thu, 05 May 2011 13:00:00 GMT

The announcement of the Cadence Virtual System Platform is a momentous event for me. Anybody who has been reading my blog knows I have been interested in virtual platforms for a long time. Since my days as a young engineer trying to debug Pentium CPU...(read more)

Building Open Virtual Platforms - Bridging the Gap of Model Availability

Steve Brown — Wed, 04 May 2011 13:00:00 GMT

Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing...(read more)

The Challenge of System Integration and Bring-Up

Ran Avinun — Tue, 03 May 2011 22:00:00 GMT

In the last few years, I have talked with many companies and analysts and consistently heard that system integration time is becoming one of the key challenges in system development. Many companies spend 50% of their total development cycle on system...(read more)

Combating System-Level Design Confusion

jasona — Mon, 11 Apr 2011 13:00:00 GMT

I would like to add my thanks to Gary Smith for his short "Industry Note" titled " ESL Behavioral Design " that I first saw in a post by Steve Leibson . Yes, the note is pretty short and topic is pretty broad, but the diagram and definitions...(read more)

DATE Spotlights System Development University Investment in Europe

Steve Brown — Thu, 10 Mar 2011 21:00:00 GMT

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's attending the University Booth at the DATE Conference in Grenoble, France March 14-18. I’m getting ready for a busy upcoming week with DATE conference in Grenoble...(read more)

Do You Have a DATE with Software? Cadence Does!

Steve Brown — Mon, 28 Feb 2011 14:00:00 GMT

How important is the software market to Cadence and as an element of the EDA360 vision? Important enough that Cadence is sponsoring several relevant sessions at the upcoming Design, Automation, and Test in Europe (DATE) conference in Grenoble, March 14...(read more)

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

Steve Brown — Thu, 24 Feb 2011 17:00:00 GMT

Don't lose touch with what's new in the world of SystemC! Cadence is a long time contributor and sponsor of SystemC initiatives, and that commitment continues to show during next week's SystemC Day and North American SystemC User Group (NASCUG...(read more)

The Increasing Role of SystemC in System Design

jasona — Tue, 22 Feb 2011 22:00:00 GMT

Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on. As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineers...(read more)

Why the Demand for Acceleration and Emulation is Growing

Ran Avinun — Mon, 14 Feb 2011 22:00:00 GMT

The dream of any marketer is a growing demand for its product line. Let me start this blog by quoting the System Realization (part of the Cadence EDA360 strategy) section from the transcript of the recent (Q4) Cadence earnings call. "In April (2010...(read more)

De-Mystifying SystemC: What is TLM?

Jack Erickson — Thu, 03 Feb 2011 21:00:00 GMT

In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of the block...(read more)

SystemC: It's Neither Complicated Nor Belligerent!

Jack Erickson — Mon, 24 Jan 2011 14:00:00 GMT

I was recently talking to a customer who was looking to move up in abstraction from RTL to SystemC for all the usual good reasons (increased verification productivity, broader micro-architecture exploration, easier re-use, etc). However he was concerned...(read more)

System Realization Webinars in 2010 -- A Summary

MayankBhatia — Fri, 07 Jan 2011 21:00:00 GMT

Last year was unprecedented for Cadence. We came up with the EDA360 vision , reorganized internally to align to that vision, and established some great partnerships to help our customers realize their own visions around EDA360. The ED360 vision paper...(read more)

More on the SystemC ARM Linux Boot Loader

jasona — Mon, 03 Jan 2011 14:00:00 GMT

My last post described a Linux Loader for ARM Virtual Platforms . Taking a closer look at the code you will see that it's not completely reusable for any ARM design. One of the hard-coded things is the board id. The version I posted has a board id...(read more)

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part II)

Ran Avinun — Tue, 28 Dec 2010 14:00:00 GMT

2010 was a very dynamic year for the electronic systems industry overall and Cadence in particular. In this set of blogs, I discuss some of the trends that started in 2010 and will continue in 2011. In part I, I talked about the key growth market, key...(read more)

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

Ran Avinun — Thu, 16 Dec 2010 14:00:00 GMT

2010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I...(read more)

On-Demand Webinar: TLM Design and High-Level Synthesis

Jack Erickson — Tue, 14 Dec 2010 18:00:00 GMT

In case you missed it last week, Mark Warren delivered a very informative webinar over at EETimes TechOnline, on migrating to Transaction-Level Model (TLM) design and using high-level Synthesis. Fortunately, this webinar was recorded and is available...(read more)

A SystemC TLM 2.0 ARM Linux Boot Loader

jasona — Wed, 08 Dec 2010 17:00:00 GMT

Earlier this year I wrote an article with some details related to loading Linux into memory for Virtual Platform execution. I reviewed a problem related to Ubuntu on qemu for the ARM Versatile Platform. At Cadence, we are strong believers in standards...(read more)

Evolution and Synthesis

Jack Erickson — Mon, 29 Nov 2010 17:00:00 GMT

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over at EE Times entitled "The evolution of design methodology" (part 1) . Their conclusion is that the chip design industry is in the midst of another major shift...(read more)

Broadcom Presentation Shows Value of Transaction-Based Acceleration

rmathur — Tue, 16 Nov 2010 14:00:00 GMT

Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom and Cadence, titled Transaction-Based Acceleration: Strong Ammunition in any Verification Arsenal , showed evidence that simulators are running out of steam for system...(read more)