The Zynq Virtual Platform: Not Just for Pre-Silicon
By Jason Andrews
on February 7, 2012
One of the biggest misconceptions about Virtual Platforms is that they are only useful for pre-silicon software development, and once a chip and board is ready they are quickly discarded. Even after boards are available, Virtual Platforms are valuable...
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Filed under: embedded software, linux, SystemC, virtual platforms, virtual prototypes, Virtual System Platform, Zynq, Zynq-7000', Watchdog Timer, pre-silicon, post-silicon
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System-Level Design and the Waves of EDA
By Frank Schirrmeister
on January 30, 2012
Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago. 2011 was an interesting year for system...
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Filed under: ESL, software, Virtual Platforms, virtual prototypes, abstraction, IP assembly, IP integration, IEEE Spectrum, VSI, Schirrmeister, automobiles, 1997, ESL system-level design, cars, EDAC, VCC
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Creating the Zynq Virtual Platform, Including Errata
By Jason Andrews
on January 6, 2012
Although I have never contributed any code to the Linux kernel, the headline We are all Linux developers now on linux today caught my eye. One of the things that amazes me is how many embedded products use Linux and how they deal with all of the complexity...
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Filed under: embedded software, linux, SystemC, ip-xact, System Design and Verification, virtual platforms, Embedded Linux, Virtual System Platform, virtual prototoypes, Zynq, errata
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Ubuntu Updates for 2012
By Jason Andrews
on January 2, 2012
I'm overdue to provide an update on how to run Virtual System Platform (VSP) and Incisive on the latest version of Ubuntu . My last article was very helpful to many people and users provided additional insight about what worked for them. Just before...
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Filed under: Incisive, SystemC, System Design and Verification, Virtual Platforms, Ubuntu, GDB, Virtual System Platform, VSP, Zynq, VirtualBox
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TLM: The Year in Review, and Trends for 2012
By Jack Erickson
on January 2, 2012
2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally...
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Filed under: Hardware/software co-verification, High-Level Synthesis, verification, SystemC, TLM, ASIC, hls, C-to-Silcon, TSMC, System Realization, C++, system design
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One Oil Change and Update my Car to the Latest Software Patch, Please!
By Frank Schirrmeister
on December 20, 2011
Since the IEEE Spectrum article "This Car Runs on Code" back in February 2009, my interest in the requirements for software and system-level development in automotive applications has grown quite a bit. And after recently having reviewed in...
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Filed under: Infineon, virtual platforms, virtual prototypes, System-Level Design, edaForum, Design Flows, embeded software, Automotive, V-Diagram, Freescael, Bosch, Engine Control Unit, ECU
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High Level Synthesis for a Control-Dominated Design?
By Jack Erickson
on December 15, 2011
CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences...
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Filed under: High-Level Synthesis, SystemC, FPGA, hls, System Design and Verification, CDNLive!, C to Silicon, CDNLive, Freescale, control-dominated, control
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Equine Anatomy, Pax Romana and the Reach of Standards
By Frank Schirrmeister
on December 14, 2011
At the recent Synopsys EDA Interoperability Forum, the opening session focused on a 10 year review of standards and interoperability between EDA tools. Three speakers -- Philippe Magarshack (Central R&D Group VP, STMicroelectronics), John Goodenough...
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Filed under: Acceleration, ESL, architect, embedded software, SystemC, TLM, osci, interoperability, high level synthesis, System Design and Verification, system, virtual platforms, IP, Hogan, system design, Accellera, Jim Hogan, standards, markets, Goodenough, pax romana, SoC Realization, Magarshack, horses
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How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
By Jack Erickson
on November 22, 2011
During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately...
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Filed under: System Design and Verification, C-to-Silicon Compiler, High-Level Synthesis, IP re-use, SystemC, TLM, C-to-Silcon, IP, reuse, re-use
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Will Software Development Cause Another “Industrial” Revolution?
By Frank Schirrmeister
on November 21, 2011
As you have read here before, Cadence has been working closely with Xilinx to create an extensible virtual prototype for the Zynq extensible platform . I have previously written about the need and value for extending virtual platforms at the transaction...
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Filed under: Virtual Platforms, virtual prototypes, System-Level Design, edaForum, Zynq, Design Flows, Industrial Automation, Siemens, Sanitas, industrial
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