Virtualization and Verification With Posedge Software
By Jason Andrews
on November 19, 2008
Posedge Software is a Cadence Verification Alliance Member with skills in two of my favorite areas: virtualization and embedded software verification. Posedge has worked with ISX as far back as 2006. Besides the fact that they are skilled in verification...
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Filed under: System Design and Verification, QEMU, OVP, open virtual platforms, posedge
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Portable Design Names Cadence Incisive Palladium Dynamic Power Analysis its September 2008 Product of the Month
By Ran Avinun
on November 4, 2008
In his article in Portable Design, John Donovan wrote: Palladium Dynamic Power Analysis represents a methodology shift for power budgeting of electronic devices with system-level implications. With a focus on productivity improvement, DPA helps to quickly...
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Filed under: System Design and Verification, Palladium, Portable Design
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The Power of Cadence System Power Flow vs. Viewing from the Top
By Ran Avinun
on October 29, 2008
I feel that I must respond to the following blog published by Frank Schirrmeister. Virtual prototypes clearly have their value and their place in the SoC design flow (especially as platforms for software development) but they are hardly a substitute for...
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Filed under: System Design and Verification, Frank Schirrmeister, power engineer, Palladium, C-to-Silicon, Incyte Chip, Incisive Enterprise Simulator, Power Analysis
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ESC Boston: Day 2
By Jason Andrews
on October 29, 2008
This morning before heading to ESC it dawned on me that the park across the street from my hotel was the Boston Public Garden . Maybe it was the swans on the hotel logo, but the ironic thing is that the only way I knew about this park was by reading the...
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Filed under: System Design and Verification, ISX, ESC, Coverage Driven Verification
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Virtualization Taxonomy
By Jason Andrews
on October 28, 2008
I arrived safe and sound at the Embedded Systems Conference in Boston today. It's been a few years since I have attended ESC, but it all came back to me quickly, and is just as I remember it, a lot of small booths with vendors showing small boards...
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Filed under: System Design and Verification, Embedded Systems Conference, taxonomy, real-time systems, ESC, VM ware, virtualization
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Is Host-Code Execution History?
By Jason Andrews
on October 17, 2008
Before getting into the details of today's topic I'm happy to report a brand new baby girl was born on October 1 into the Andrews family of Ham Lake, MN. She is our sixth child, and the forth girl to go along with two boys. Currently, I play a...
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Filed under: System Design and Verification, QEMU, Cisco, MIPS, ARM, Palladium, Verilog, Sun, OVP, Virtutech
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Early Embedded Systems Conference Coverage
By Jason Andrews
on October 13, 2008
Today, a friend sent me a link to an article on embedded.com that talks about my upcoming presentation at the Embedded Systems Boston Conference . I love the title about turning hardware and software design upside down. I guess it's true that this...
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Filed under: System Design and Verification, Embedded Systems Boston Conference
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System-level design and verification - at the center!
By Ran Avinun
on October 7, 2008
This year, Cadence increases its focus on system-level design and verification events. During the latest CDNLive San-Jose that was held in September, the guest keynote - Dr. Jan Rabaey, Distinguished Professor of Electrical Engineering at the University...
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Filed under: System simulation and analysis, System Design and Verification, Acceleration, Emulation, Hardware/software co-verification, ESL handoff, ISX, CDNLive! Silicon Valley 2008, Coverage Driven Verification for Embedded Software, ESL, embedded SW engineer, architect, embedded software
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Power Aware Design Now at System Level
By Ran Avinun
on October 6, 2008
Several years ago, I have purchased a cell phone with a 2 years contract from one of the major wireless service providers in the US. The battery lifetime between charges of this phone was terrible - 24 hours. The service provider promised me that there...
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Filed under: System simulation and analysis, System Design and Verification, Acceleration, Hardware/software co-verification, Low power verification and analysis, Verification Acceleration, Simulation Acceleration, C-to-Silicon Compiler, debugging, ESL, system validation/verification engineer, embedded SW engineer, architect
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The cell world
By Ran Avinun
on September 24, 2008
Earlier this Summer, I was lucky enough to attend the CDNLive show in Japan. One of the keynote speakers at the show was Mr. Mitsuo Saito, Chief Fellow at Toshiba Corporation Semiconductor Company. Mr. Saito-san delivered a presentation about the 20 years...
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Filed under: Sony, cell processor, IBM, Playstation, Toshiba
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