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System Design and Verification Blog

The webinar on “Effective system-level coverage” does an effective coverage of the talk

If you're anything like I am, you listen to webinars with one ear, occasionally checking your computer screen if a graph or image is referenced, perhaps catching up on email or articles while the webinar is running in the background. I have always...  Read More »
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Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption Kits

The state-of-the-art Palladium XP hardware/software verification computing platform unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity. As impressive as the platform...  Read More »
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DAC 2014—ESL Design Is Dead... Long Live ESL!

Next week the EDA industry is getting together in San Francisco for Design Automation Conference 2014. As I pointed out in a recent blog called " Confessions of an ESL-Aholic ", the scope of electronic system level (ESL) design has changed quite...  Read More »
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The Importance of Ecosystems in the Internet of Things Era

As we develop electronics in early 2014, the battle between processor architectures is raging in all spaces, from deeply embedded through mobile to servers. Choosing the right ecosystem partners is crucially important, and today's announcement of...  Read More »
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Recap of Another Successful Japan C-to-Silicon User Seminar

Back in November, our Japan office hosted a C-to-Silicon Compiler user meeting. They host about two per year, and the meetings have been growing in size and content. The November session drew 44 customers, representing 13 companies. The content spanned...  Read More »
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New Capabilities in the C-to-Silicon Compiler 2013 Releases

2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular. We saw our customers take on over 75 new projects using C-to-Silicon, much of that coming from expanded adoption within our existing customers. These designs spanned...  Read More »
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Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit

Code coverage is an effective tool in the verification process, giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time-consuming...  Read More »
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High-Level Synthesis Now Spans the Datapath-Control Spectrum

When we talk to prospective high-level synthesis (HLS) customers, one of the slides we show is a pie chart that breaks down the types of production designs (that we are aware of) for which customers have used C-to-Silicon Compiler. The current snapshot...  Read More »
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High-Level Synthesis—What Expertise Is Needed for Micro-Architecture Tradeoffs?

My most recent blog post mentioned how utilizing new algorithms together with high-level synthesis can continue to drive innovation in hardware design by balancing power consumption with performance improvements. A great example of this is what Fujitsu...  Read More »
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Accelerated Code and Functional Coverage Using Palladium XP

Code coverage is an effective tool in the verification process—giving insights into testing completeness as well as identifying highly active or inactive areas of a design. Collecting code coverage in simulation on large designs can be a very time...  Read More »
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