Emulation Is Here To Stay
By Ran Avinun
on November 2, 2009
A recent blog by Brian Bailey covered the emulation war. I would like to correct some of the facts Brian has mentioned and also add my own comments. First, Brian, you owe Cadence an apology :) You forgot some of the emulation announcements from Cadence...
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Filed under: System Design and Verification, Emulation
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From Cadence Earning Call This Week
By Ran Avinun
on November 2, 2009
In system development, we have focused on two key customer challenges. First, we are increasing their productivity by elevating design and verification to the next level of abstraction. This quarter, we announced the industry’s first transaction...
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Filed under: System Design and Verification, OVM, TLM, ITRI, Nethra Imaging, Silicon Hive, nVidia, Schwartz, Rhode
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Improve Productivity Through Communication and Learning
By Jason Andrews
on November 2, 2009
I regularly spend time talking to people about the importance of the connection between embedded software and hardware design and verification. If you have been following my writing on cadence.com you know that it takes more than tools to succeed on a...
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Filed under: System Design and Verification, ISX, Virtual Platforms, CDNLive! 2009 Silicon Valley
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4G Is Here Now
By Ran Avinun
on October 27, 2009
If you have not heard about 4G yet, it is here now. Verizon has already paid earlier this year $9.4B for an open access to the new spectrum. It'll be using the spectrum as the core of their high-speed 4G LTE network - see below. http://gizmodo.com...
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Filed under: System Design and Verification, Wimax, 4G, Rohde & Schwarz, mobile, Verizon
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Keeping Trident Missiles "On Target" With System-Level Verification
By Steve Svoboda
on October 23, 2009
Can you think of a more critical application for system-level verification than making ABSOLUTELY CERTAIN a missile carrying nearly 5 Megatons of nuclear payload doesn't have any "bugs"? We've all seen enough James Bond and Superman...
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Filed under: System Design and Verification, Palladium, TLM, Mil-Aero, Draper Labs
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Synopsys’ “Synphony” Announcement – Welcome to the Party!
By Steve Svoboda
on October 14, 2009
I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge productivity...
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Filed under: System Design and Verification, verification, ESL, RTL, TLM
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Webcast: EDA, ESL and More Ideas From DAC
By Jason Andrews
on October 13, 2009
From the events calendar, OpenSystems Media is hosting a webcast tomorrow titled EDA, ESL, and More Ideas from DAC that will be hosted by Don Dingee and feature presentations and discussion from Frank Schirrmeister from Synopsys, Shabtay Matalon from...
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Filed under: System Design and Verification, ISX, ESL, PMC Sierra, Virtual Platforms, OpenSystems
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Virtualization and Simulation Roundtable
By Jason Andrews
on October 13, 2009
A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com . Please have a look if you are interested in Virtual Platform usage for embedded software. One of the things that...
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Filed under: ARM, Palladium, virtualization, VMware, System Design and Verification, EDA Cafe, Virtual Box
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Intrusive Software Debugging: Friend or Foe?
By Jason Andrews
on October 6, 2009
One of the great benefits of working with simulation (RTL, SystemC , or any Virtual Platform) is the ability to provide non-intrusive interactive software debugging. Interactive software debugging provides the control and data access needed to inspect...
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Filed under: System Design and Verification, debugging, virtual platform, SystemC, TLM 2.0 Trace, Co-verification
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Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!
By Steve Svoboda
on October 3, 2009
Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009 . With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attendance than back...
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Filed under: System Design and Verification, IBM, ARM, C-to-Silicon, SystemC, TLM, PMCS, TI, Vittuatech, CDNLive!, DAC&V, CoWare
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