System Design and Verification

The Zynq Virtual Platform: Not Just for Pre-Silicon

2012-02-08T04:29:00Z

One of the biggest misconceptions about Virtual Platforms is that they are only useful for pre-silicon software development, and once a chip and board is ready they are quickly discarded. Even after boards are available, Virtual Platforms are valuable for software development. Last week I was talking with an engineer at a company that is working on a new system design and has started Virtual Platform development. He told me that one of the software engineers was working on a demo to showcase their...(read more)

System-Level Design and the Waves of EDA

2012-01-30T17:00:00Z

Before January comes to an end it is time for my annual flashback and brief reflection on where we are in system-level design, and a look at how the state of today compares to the predictions we made 10 years ago. 2011 was an interesting year for system-level design. In May Cadence announced its participation in the system-level domain with the System Development Suite. The year before, in 2010, we had seen consolidation in the virtual platform space with Synopsys picking up VaST, CoWare and Synfora...(read more)

Creating the Zynq Virtual Platform, Including Errata

2012-01-06T17:00:00Z

Although I have never contributed any code to the Linux kernel, the headline We are all Linux developers now on linux today caught my eye. One of the things that amazes me is how many embedded products use Linux and how they deal with all of the complexity. Nearly every product has similar but different hardware, and keeping it all straight and shipping a product with working software in the dynamic world of Linux is impressive. As a virtual platform developer these details hit me every so often...(read more)

Ubuntu Updates for 2012

2012-01-02T17:00:00Z

I'm overdue to provide an update on how to run Virtual System Platform (VSP) and Incisive on the latest version of Ubuntu . My last article was very helpful to many people and users provided additional insight about what worked for them. Just before the holiday break we delivered our latest version of the Zynq Virtual Platform to some early beta users. One of the delivery options we have been using is to deliver a Virtual Machine with all of the software pre-installed and configured so it's...(read more)

TLM: The Year in Review, and Trends for 2012

2012-01-02T14:00:00Z

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream, delivering the benefits that have been sought for years. Has this methodology started to become mainstream? I think it's safe to say that it has started. We have been working with some large...(read more)

One Oil Change and Update my Car to the Latest Software Patch, Please!

2011-12-20T19:00:00Z

Since the IEEE Spectrum article "This Car Runs on Code" back in February 2009, my interest in the requirements for software and system-level development in automotive applications has grown quite a bit. And after recently having reviewed in previous blog posts requirements for wireless and industrial applications, automotive seems to be a great next topic. According to market data provided by dataBeans in July this year, the automotive segment is actually expected to be in 2011 the smallest...(read more)

High Level Synthesis for a Control-Dominated Design?

2011-12-15T18:18:00Z

CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you are a registered attendee, you can access papers with your CDNLive! login. One paper I'd like to highlight is from the CDNLive! India conference in Bangalore back in October. Manoj Sharma and Deepak...(read more)

Equine Anatomy, Pax Romana and the Reach of Standards

2011-12-14T14:00:00Z

At the recent Synopsys EDA Interoperability Forum, the opening session focused on a 10 year review of standards and interoperability between EDA tools. Three speakers -- Philippe Magarshack (Central R&D Group VP, STMicroelectronics), John Goodenough (Vice-President of Design Technology and Automation, ARM) and Jim Hogan (Private Investor) -- reviewed their predictions from roughly ten years ago, and commented on how standards have evolved since then and whether and how they enabled the interoperability...(read more)

How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

2011-11-22T14:00:00Z

During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately titled "Make vs. Buy". I won't re-hash it here, though I might add one choice: reuse. Except for startups, most chip designs have IP internally that they can re-use from previous projects. The ability to re-use blocks is often lacking...(read more)

Will Software Development Cause Another “Industrial” Revolution?

2011-11-21T17:15:00Z

As you have read here before, Cadence has been working closely with Xilinx to create an extensible virtual prototype for the Zynq extensible platform . I have previously written about the need and value for extending virtual platforms at the transaction level . According to the Xilinx Zynq website the main application domains for Zynq are "Intelligent Video," "Comms," "Control" and "Bridging." A couple of these sub-application domains are directly targeted...(read more)

Parallel Compilation for SystemC

2011-11-17T16:00:00Z

One of the most common complaints about SystemC is that it takes too long to compile. I tend to agree that it does take longer to compile compared to C or Verilog. The primary reason is that SystemC is a somewhat complex set of libraries built on top of C++ and is compiled with g++. Almost every programming language has pros and cons, and compile time happens to be a con of SystemC. The next most common complaint after general SystemC compile time is that the utility commonly used to compile SystemC...(read more)

Welcome to the Zynq-7000 Virtual Platform

2011-10-28T15:10:00Z

As you might guess we are pretty excited about the Virtual Platform development for the Zynq-7000 EPP . The FPGA world has changed a lot from 1995 when I was an FAE at Cypress Semiconductor selling and supporting programmable logic devices. This was during the transition from schematic capture to HDLs. It was the days of PALASM and ABEL , and then the first VHDL and Verilog synthesis tools for FPGAs. Back then nobody did much simulation; after all it was a reprogrammable device (except for those...(read more)

Virtual Platform UART Use Number 4: Connecting to an RTOS Tracing Framework

2011-10-24T13:00:00Z

This is the last installment of my series on different uses for the UART in Virtual Platforms. Today's article is about how to use a UART as a way to capture logging information about a running system. One of the challenges of developing embedded software is trying to understand what is happening. Having a debugger to control the software is useful, but debuggers work at a very low level, stopping the software at defined breakpoints in specific places in the source code. Understanding the big...(read more)

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?

2011-10-04T15:00:00Z

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm. Two thoughts came to my mind: Wow! What is their ROI of migrating from an RTL-driven methodology to a SystemC-driven methodology? Thought #2 is the million-dollar question that design teams are facing today. The theoretical benefits of moving to a higher-level of...(read more)

edaForum: Evolving Devices from “All in One” to “One for All”

2011-09-26T19:00:00Z

This week I had the pleasure to attend and to present at the 11 th annual edaForum , held in Berlin, Germany. Coming back to my hometown and presenting at this conference was a real treat, even though the traffic was much worse than I remembered, mostly because on that day the Pope visited Berlin. The edaForum kicked off with a fascinating keynote given by Prof. Dr. Hermann Eul, President of Intel Mobile Communications, IMC, the former Infineon division that is now part of Intel. Dr. Eul first noted...(read more)

Virtual Platform UART Use Number 3: Using gdb to Debug a Software Application

2011-09-22T15:00:00Z

This is the next installment in my series covering the uses of the venerable UART in Virtual Platform simulation. Use the links below to review the previous articles: Introduction Connecting an xterm to a UART Using telnet to connect to a UART This article covers using gdb to debug a program running on the simulated system. The communication between gdb , running on the host machine, and the program being debugged, running on the target system, is done through the UART. To clarify, this use case...(read more)

Virtual Platform UART Use Number 2: Using telnet to Connect to a UART

2011-09-06T15:00:00Z

Welcome to the next installment in my series about different ways to use the venerable UART in Virtual Platforms. If you missed the first two parts you can review the introduction and use case 1, about using xterm in slave mode for an interactive terminal . This article explains another way to provide an interactive terminal. Instead of using the xterm in slave mode we can use a network connection and the telnet program to connect to a UART and have an interactive terminal. Recall that the UART has...(read more)

Virtual Platform UART Use Number 1: Connecting to an Interactive Terminal

2011-08-18T15:00:00Z

Welcome to the first example of using a UART in a Virtual Platform. For those just joining, I outlined a list of four UART uses in my previous introduction . One of the most common ways to use a UART in a Virtual Platform is to connect to a terminal and use it as an input and output device. When working with real hardware it's common to connect a serial cable and use various terminal emulation programs to connect to an embedded system. Commonly used programs for Windows are HyperTerminal or PuTTY...(read more)

IP Cannot be an Efficient Abstraction Level Without SystemC!

2011-08-12T18:00:00Z

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble IP from various sources into a platform, differentiate with software, and swap in different IP for derivative designs that target different requirements. It all makes sense. However, where it goes...(read more)

Virtual Flash Memory Gets Real

2011-08-08T23:00:00Z

This week's Flash Memory summit will not only highlight the IP Cadence delivers, but will touch on innovative application of virtual prototype technology for Flash Memory firmware and system development. Developing complex memory controllers is challenging, and an increasing portion of the capability is delivered as firmware. Virtual prototypes of hardware for memory controllers, and the systems within which they operate, enable software to be developed months ahead of the first RTL for simulation...(read more)

A Must Read: the ARM Cortex-A Programmer's Guide

2011-08-04T20:00:00Z

For the last couple of years, I have been getting a lot of e-mail from different LinkedIn groups. I'm interested in groups like Android, Embedded Linux, ARM, EDA Bloggers, and more. A majority of the days I don't have time to read much (or any) of the information and end up deleting a lot of e-mail. Today, I found a wonderful link that makes all of the time spent deleting e-mail worth it. In the ARM group, I found a link to a document (really a book) called ARM Cortex-A Programmer's Guide...(read more)

Four Uses for the Venerable Virtual Platform UART

2011-07-27T17:00:00Z

The Universal Asynchronous Receiver/Transmitter (UART) is one of the oldest hardware peripherals, and yet it is is still present in many embedded systems created today. I'm not sure when it was invented, but Wikipedia says it was designed by Gordon Bell at DEC for the PDP series machines. It was present on the original IBM PC, and is still present in most SoC designs. UARTs can be found on boards like the ARM Versatile Express and Panda . Even mobile devices which don't seem to have any RS...(read more)

ARM Generic Interrupt Controller HOWTO

2011-07-22T15:00:00Z

Way back in 2004, I wrote a book called Co-Verification of Hardware and Software for ARM SoC Design . At that time the world revolved around AHB and the ARM926EJ-S was a popular CPU. All ARM CPUs used two interrupt signals, nIRQ and nFIQ . The nIRQ signal is the normal interrupt request and nFIQ is the fast interrupt request. The bus signals for these two interrupts are active low signals, so driving the signal low indicates an interrupt. The ARM architecture defined exception addresses as shown...(read more)

Creating SystemC TLM-2.0 Peripheral Models

2011-07-14T18:00:00Z

Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than time to give you an update, and the good news is that such a tool is now available as part of the new Cadence Virtual System Platform (VSP) product. One of the capabilities provided by the Virtual System Platform is a tool to enable easy authoring of Virtual...(read more)

A SystemC Virtual Platform Overflowing the Stack -- Just Before DAC

2011-06-14T16:00:00Z

Thanks to all who stopped by the Cadence booth to see and talk about the Cadence Virtual System Platform at DAC . I spent most of the week in meetings and giving presentations and demos so I don't have any insight into the virtual platform related events from the conference. Instead of writing a general report about how important virtual platforms are or how many people came to see the recently announced Virtual System Platform, I will use my DAC wrap-up for something more educational, a DAC...(read more)

Using the ARM Profiler with the Cadence Virtual System Platform

2011-06-13T16:00:00Z

I have posted a new article over at blogs.arm.com covering the current integration of the ARM Profiler with the Cadence Virtual System Platform . It's a must read for users interested in profiling software running on a virtual platform. If you have used the ARM Profiler before or have ideas on better integration, feel free to send them to me or post a comment. Thanks again to the ARM team for the great job they do publishing partner blogs. Jason Andrews...(read more)

Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!

2011-05-23T16:00:00Z

It's been an exciting month for the System Realization team with the announcement of our System Development Suite . One of the new products, the Cadence Virtual System Platform , made its debut at the Embedded Systems Conference and has generated a lot of interest from our customers. DAC is right around the corner, and we'll be there with the latest demos of the System Development Suite, and a suite demo focusing on the VIrtual System Platform on Monday at 3pm, Tuesday at 9am, and Wednesday...(read more)

Blazing a Trail With Ubuntu

2011-05-23T13:00:00Z

One of the most popular blogs I wrote is running Incisive on Ubuntu . I have had a number of questions and comments, as well as thanks for pointing out some of details on how to make everything work. One person even had the suggestion to start a user group! In the article, now over a year old, I used Ubuntu 9.10, which was probably the newest version at the time. One of the great things about Ubuntu is the rapid progress that occurs when new versions are released every six months. I thought it was...(read more)

Panel Discussion: Applying High-Level Synthesis in an SoC Flow

2011-05-16T17:00:00Z

Last Thursday, EETimes hosted a virtual System on Chip event focused on IP integration in SoCs. Even with IP re-use comprising a large percentage of new SoCs, new IP must also be developed in order to differentiate on the hardware side. With RTL containing so much application-specific implementation detail, more companies are looking to move to high-level synthesis based on SystemC, which allows for separation of pure functionality from implementation details. Five panelists took part in a discussion...(read more)

System Development Suite - Connecting Software to Hardware Design and Verification

2011-05-09T13:00:00Z

I've been at CDNLive! EMEA watching demos of the newly announced System Development suite, and it's mindblowing. I'm seeing good old ncsim running Android interactively on the Virtual System Platform. You open an app in the virtual Android interface and you can stop the software, or even the hardware model, at a breakpoint in ncsim. I'm seeing FPGA prototypes compiled at light speed with the Rapid Prototyping Platform. From a big picture perspective, Richard Goering's "The...(read more)

Yes We Can...Do FPGA-Based Prototoyping

2011-05-06T13:00:00Z

As part of this week's System Development Suite announcement , Cadence introduced two new platforms, the Virtual System Platform and the Rapid Prototyping Platform. Both new platforms help users start embedded software development much earlier, thus providing an accelerated path to revenue. I'm particularly excited about the Rapid Protoyping Platform (shown below) for multiple reasons. For one it is a natural extension and complement to our successful Verification Computing Platform, also...(read more)

Welcome to the Cadence Virtual System Platform

2011-05-05T13:00:00Z

The announcement of the Cadence Virtual System Platform is a momentous event for me. Anybody who has been reading my blog knows I have been interested in virtual platforms for a long time. Since my days as a young engineer trying to debug Pentium CPU boards running SMP Unix in the 1990's, fighting to keep the logic analyzer probes from falling off before the system would hang after hours of operation, I wanted to work on simulation models that would run real software. Through all of the early...(read more)

Building Open Virtual Platforms - Bridging the Gap of Model Availability

2011-05-04T13:00:00Z

Virtual prototypes promise to enable early software development, shorten system bring-up time, and provide a resulting increase in revenue. One of the key barriers that project teams face when considering use of virtual prototypes is the "missing model syndrome" -- essentially the lack of adequate pre-built IP to assemble into the prototype, and the challenges of creating those models themselves. Some providers have created libraries of models, but without a standard language the models...(read more)

The Challenge of System Integration and Bring-Up

2011-05-03T22:00:00Z

In the last few years, I have talked with many companies and analysts and consistently heard that system integration time is becoming one of the key challenges in system development. Many companies spend 50% of their total development cycle on system integration and bring-up. This blog will describe the key challenges customers face today, and will refer to a new Cadence approach and offerings to address them. Post-Silicon System Integration and Bring-Up The flood of application-driven devices forces...(read more)

Combating System-Level Design Confusion

2011-04-11T13:00:00Z

I would like to add my thanks to Gary Smith for his short "Industry Note" titled " ESL Behavioral Design " that I first saw in a post by Steve Leibson . Yes, the note is pretty short and topic is pretty broad, but the diagram and definitions of Silicon Virtual Prototype (SVP) and Software Virtual Prototype (SWVP) are a big help by themselves. System-level design is complex because it involves a number of different use cases that have different goals and requirements, but are closely...(read more)

DATE Spotlights System Development University Investment in Europe

2011-03-10T21:00:00Z

In this guest blog Markus Winterholer, R&D engineer at Cadence, explains why he's attending the University Booth at the DATE Conference in Grenoble, France March 14-18. I’m getting ready for a busy upcoming week with DATE conference in Grenoble, France. Besides organizing a workshop and a panel about embedded system debug and test, presenting Cadence ESL tools at the Europractice event and helping representing Cadence at GlobalFoundries (booth 1& 2), I’m squeezing customer...(read more)

Do You Have a DATE with Software? Cadence Does!

2011-02-28T14:00:00Z

How important is the software market to Cadence and as an element of the EDA360 vision? Important enough that Cadence is sponsoring several relevant sessions at the upcoming Design, Automation, and Test in Europe (DATE) conference in Grenoble, March 14-18, 2011. If you're anywhere near Grenoble in March, these are must-see events! First there is a panel on the confluence of virtual platforms, the use of IP-XACT for assembly, and their potential for changing the RTL-based SoC design flow, on Tuesday...(read more)

Cadence Investment in SystemC Continues -- NASCUG SystemC Day at DVCon

2011-02-24T17:00:00Z

Don't lose touch with what's new in the world of SystemC! Cadence is a long time contributor and sponsor of SystemC initiatives, and that commitment continues to show during next week's SystemC Day and North American SystemC User Group (NASCUG) at DVCon . The conference is being held at the DoubleTree hotel in San Jose, California, February 28th-March 3rd. Cadence has been involved in SystemC initiatives for so long I sometimes forget that not everyone knows the extent of our involvement...(read more)

The Increasing Role of SystemC in System Design

2011-02-22T22:00:00Z

Today's post is less technical and a bit more theoretical, but I promise that my next post will be more hands-on. As somebody working on virtual platforms in an EDA company, I regularly spend time talking to firmware and embedded software engineers with many different backgrounds. Every so often one of them asks, "Why SystemC?" Some software engineers look at SystemC and decide that it looks like a real mess. They mention things like: SystemC has complex classes built with C++ It uses...(read more)

Why the Demand for Acceleration and Emulation is Growing

2011-02-14T22:00:00Z

The dream of any marketer is a growing demand for its product line. Let me start this blog by quoting the System Realization (part of the Cadence EDA360 strategy) section from the transcript of the recent (Q4) Cadence earnings call. "In April (2010), we introduced the Verification Computing Platform, enabling emulation, acceleration, and simulation all on one single platform. Customers who are designing SoCs at 40nm and below find this product necessary to meet the time-to-market and quality...(read more)

De-Mystifying SystemC: What is TLM?

2011-02-03T21:00:00Z

In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of the block from the way it interfaces to the system. So if you were designing an MPEG decoder, the decoding algorithm would be the core functionality. If it used AXI to communicate with the system, the AXI protocol would be the interface. You can then describe...(read more)

SystemC: It's Neither Complicated Nor Belligerent!

2011-01-24T14:00:00Z

I was recently talking to a customer who was looking to move up in abstraction from RTL to SystemC for all the usual good reasons (increased verification productivity, broader micro-architecture exploration, easier re-use, etc). However he was concerned that the learning curve for his team would be too high. He specifically referenced an article by one of our competitors that positioned SystemC as something different from C++ (and according to the article was apparently once at war with it), and...(read more)

System Realization Webinars in 2010 -- A Summary

2011-01-07T21:00:00Z

Last year was unprecedented for Cadence. We came up with the EDA360 vision , reorganized internally to align to that vision, and established some great partnerships to help our customers realize their own visions around EDA360. The ED360 vision paper has been well received by both customers and competition, giving further validation to the concept. One of the premises of the paper is that software applications (or "apps") are taking precedence over the hardware. Applications such as social...(read more)

More on the SystemC ARM Linux Boot Loader

2011-01-03T14:00:00Z

My last post described a Linux Loader for ARM Virtual Platforms . Taking a closer look at the code you will see that it's not completely reusable for any ARM design. One of the hard-coded things is the board id. The version I posted has a board id of 0x113, which happens to be for the ARM Integrator CP board. For another system, this field would have to be changed. For example, the Android Goldfish platform , which is not an actual board, but a hypothetical system modeled by the Android emulator...(read more)

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part II)

2010-12-28T14:00:00Z

2010 was a very dynamic year for the electronic systems industry overall and Cadence in particular. In this set of blogs, I discuss some of the trends that started in 2010 and will continue in 2011. In part I, I talked about the key growth market, key industry challenges and the role of EDA. In this blog post (part II), I will talk about Cadence offerings addressing these challenges. Cadence System Design and Verification -- Addressing IP Productivity and System Integration In order to be successful...(read more)

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

2010-12-16T14:00:00Z

2010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I will talk about the key growth markets, key industry challenges, and the role of EDA. In the next blog (part II), I will talk about Cadence offerings addressing these challenges. Key Growth Market -- Application-Driven Internet Mobile The introduction...(read more)

On-Demand Webinar: TLM Design and High-Level Synthesis

2010-12-14T18:00:00Z

In case you missed it last week, Mark Warren delivered a very informative webinar over at EETimes TechOnline, on migrating to Transaction-Level Model (TLM) design and using high-level Synthesis. Fortunately, this webinar was recorded and is available on-demand here: Practical application of high-level synthesis in SoC designs This 1-hour presentation covers the following topics, along with some good Q&A at the end: The benefits of moving to TLM-driven design and verification Cadence C-to-Silicon...(read more)

A SystemC TLM 2.0 ARM Linux Boot Loader

2010-12-08T17:00:00Z

Earlier this year I wrote an article with some details related to loading Linux into memory for Virtual Platform execution. I reviewed a problem related to Ubuntu on qemu for the ARM Versatile Platform. At Cadence, we are strong believers in standards, and for Virtual Platforms one of the key standards is SystemC TLM 2.0 . Since more and more companies are adopting SystemC for Virtual Platform development I thought it might be useful for readers to look at the Linux loading process from a SystemC...(read more)

Evolution and Synthesis

2010-11-29T17:00:00Z

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over at EE Times entitled "The evolution of design methodology" (part 1) . Their conclusion is that the chip design industry is in the midst of another major shift to one where chip design becomes software-centric. In other words, system houses define the end-product, and much of the differentiation now comes from software. This software lives on across multiple generations of SoC's. So they are building SoC's...(read more)

Broadcom Presentation Shows Value of Transaction-Based Acceleration

2010-11-16T14:00:00Z

Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom and Cadence, titled Transaction-Based Acceleration: Strong Ammunition in any Verification Arsenal , showed evidence that simulators are running out of steam for system level simulations. At Broadcom, simulators certainly maintain their value from sub-block to chip-level simulations, providing their users with tremendous debug and ease-of-use efficiencies. However, the lowered performance profile for simulations at...(read more)