System Design and Verification

Industry Standard SystemC is What Designers Want

2009-07-03T08:00:00Z

This past Monday saw not one HLS related announcement but two...this space is really heating-up! Mentor’s Catapult announced support for control-logic design, and clock-gating (to reduce power) and Forte announced a new release with some minor new features. Today, I'll focus on Catapult, since their direction seems the most interesting in my view. Mentor is promoting ANSI-C as their HLS input language with extensions into ANSI-C to create a "lightweight" (and Mentor proprietary...(read more)

DAC Virtual Platform Workshop

2009-06-30T15:00:00Z

Back in early May, I wrote that it was Not Too Early to Start Thinking About DAC 2009 . Well, now it is too late to start thinking about it, and it is time to start acting by making plans to get to San Francisco. One of the events I will attend is the Virtual Platform Workshop . Workshop organizer Soha Hassoun recently posted an article on Gabe on EDA that raises some interesting questions. Trying to blend the world of chip design with embedded software is a topic that comes up over and over for...(read more)

The Golden Age of Electronics

2009-06-26T14:07:00Z

About a month ago I took my family to The Bakken Museum in Minneapolis, Minnesota. We wanted to visit the museum for some time, but never made quite it. We even went there once last year only to find out it is closed every Monday. The history of the museum derives from from Earl Bakken, a co-founder of Medtronic in 1949. It's a great place for kids to learn some of the history of medical electronics, and also more about the general role of electricity in our lives. As you enter the museum area...(read more)

Speeding up SystemC compilation with Incisive SystemC

2009-06-19T13:00:00Z

If you’re a C++ and SystemC programmer you know that when you’ve spent all day tracking down a nasty bug, nothing can bum your trip more than having to wait around for a long recompile. Compile time is a bottleneck for SystemC development. Long compile times can come as a particular surprise for HDL programmers who aren’t used to the lag time caused by template instantiation, dependency checking, and the mysterious thinking that goes on the in the guts of g++ as it creates object...(read more)

OVM Metric Driven Verification With an FPGA-based Design

2009-06-17T19:30:00Z

During the last 2 years I have enjoyed the opportunity to work with the Incisive Software Extensions (ISX) with many customers. I learned a lot about software/hardware co-verification and we reached the point were we started to see beyond one’s own nose. One of the substantial concepts of ISX is the generic software adapter. The accentuation here is the attribute 'generic'. The generic approach guaranties the freedom to connect almost everything that somehow drives embedded software...(read more)

The DWARF Debugging File Format

2009-06-12T18:00:00Z

The Chronicles of Narnia has always been one my favorite series of books. Today, I'm not going to talk about dwarfs such as Trumpkin , the dwarf that appeared in Prince Caspian ( check out the latest movie ), but instead something called the DWARF Debugging Standard . DWARF is a file format used by compilers and debuggers to enable source level debugging. A compiler writes information into a generated executable file and a debugger reads the information so that when the program is run it can...(read more)

Synthesis Really DOES Need to Change

2009-06-02T13:00:00Z

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, “ Synthesis Needs to Change to Serve Modern Chip Design ”. Tets Maniwa is sharp guy. (Those of you designing ICs in the mid/late 1990s probably remember a wonderful magazine called “Integrated System Design” (ISD). ISD was one of the premier IC design trade-pubs around at the time, and Tets was lead editor.) Whenever Tets writes something, it’s worth reading. The thesis of Tets’ article...(read more)

Where's the Bridge to Cross the Great Divide?

2009-05-28T13:00:00Z

At this year's Embedded System Conference in San Jose there was a panel with the title Who's Taking over Whom - Is EDA Moving into Embedded or Embedded into EDA? One of the analogies Mike McNamara from Cadence used was hardware and software engineers on opposite sides of a river wondering how to construct a bridge to the other side while sharks swim in the water separating them. It reminded me of a song from a group called Point of Grace titled "The Great Divide" (track 8 on the...(read more)

Way Worse Than The Real Thing

2009-05-19T04:05:00Z

This week Cadence and Virtutech announced a collaborative effort to bring together the Virtutech Simics virtual platform with the Cadence ISX software testing system. This is a very interesting combination of technologies, clearly demonstrating how virtual platforms make it possible to test software in ways that are plain impossible on physical hardware. With a virtual platform, it is possible to systematically subject a system software stack to extreme (and normal) working conditions, trying to...(read more)

ESL Verification News From CDNLive! EMEA

2009-05-19T01:00:00Z

Hello from CDNLive! EMEA in Munich. Another year has passed, and it’s time again for one of the most popular CDNLive! tour stops here in EMEA. The location is the beautiful European city of Munich , at the Park Hilton Hotel . The hotel overlooks one of the largest urban parks called the English Garden , and the weather this year has yielded lush and vigorous foliage at every corner, and throughout the park. This peaceful setting will lull even the most ardent technologist into a much needed...(read more)

System D&V at CDNLive! EMEA

2009-05-18T23:17:00Z

CDNLive! EMEA has started today. I arrived here (Munich Germany) from SFO paying $340 for a round trip (record low for trip to Europe). Someone told me today the reason for this was that I have made my reservation at the same time the swine flu news were at their peak and with the decrease in demand for flights the tickets prices went down (go figure!). I like to start with one piece of good news. On my way to the airport the taxi driver told me that in the last month, his business started to recover...(read more)

SystemC Debug: A Summary of Summary Probes

2009-05-15T13:00:00Z

SystemC goes well beyond generic C and C++ to provide a number of semantic constructs that are essential for system-level modeling, design and verification. Among the most powerful of these are threading and concurrency. Using threading is required in order to represent concurrent systems, whether for modeling a system-on-chip, or creating a verification environment with concurrent sequences streaming across multiple interfaces. But with this power comes responsibility. Threading, when used incorrectly...(read more)

ISX Presentations at CDNLive! Munich

2009-05-13T15:45:00Z

As we head into next weeks CDNLive! event in Munich it's great to see today's post in the Industry Insights area by Richard Goering on the Embedded Software Challenge . It provides concrete data on the rising costs of embedded software design and verification for those who have been wondering if I have been crying wolf for what is now approaching one year of blogging. In fact, the article by Richard connects back to my very first post on cadence.com that summarizes the dramatic change that...(read more)

Modeling Interfaces with C-to-Silicon Compiler

2009-05-07T13:15:00Z

Users of ESL tools are curious about the procedure for handling the interface to a bus or other communicaton protocol in a High Level Synthesis environment. This is usually formulated in the following question: “How do we take into account the interface to the bus/processor for a piece of IP going into C-to-Silicon Compiler ?” There are two ways of addressing this issue using CtoS. The first option is to model the interface at the signal level using sc_signals. For example, a simple request...(read more)

Tracing TLM 2.0 Activity in an ESL Design – Part 3

2009-05-07T13:00:00Z

Last time I discussed how to use –sctlmrecord to produce an SST2 database of TLM 2.0 transaction data ( http://www.systemc.org ). In this post, we’ll explore the data in the Simvision Waveform Viewer, the Transaction Explorer, and with TxE. This is the first step towards tying TLM 2.0 trace data to TLM 2.0 debug, a topic I’ll explore in greater detail in future entries. The example can be found in an IUS 8.2 install at `ncroot`/tools/systemc/examples/tlm2/tutorial. If you want to...(read more)