System Design and Verification

Android System Verification Part 2

2009-11-13T14:00:00Z

In Part 1 of this series on Android System Verification I provided the basics about how to run the Android emulator. When I initially looked at the emulator I was looking for information about available verification techniques, primarily at the system level. I surmised that many Android projects aggregate the available software, add some new custom software to support a specific hardware platform, enable the wide range of available applications, and put all of this together to create a product. Android...(read more)

We and Our Competitors Agree (Well, Almost!)

2009-11-12T14:00:00Z

It’s rare in EDA to see competitors agreeing, but an interesting article in EEtimes Europe this week caught my eye, by Lauro Rizzatti the VP Mktg of EVE. Lauro discussed a survey EVE ran during DAC, where they asked customers how they felt about the current state of hardware-assisted verification, what their priorities were, etc. One paragraph really stood out (emphasis mine): “More interesting was the ranking of six criteria in selecting the next hardware-assisted verification platform...(read more)

Android System Verification Part 1

2009-11-09T14:00:00Z

From time to time I hear or read stories about how engineers find ways to apply Specman to verification problems that are outside of normal RTL verification. Often times they are about connecting Specman to a post-silicon environment such as a physical board. There are probably many of them, but a quick search on cadence.com turned up one published by Intel in 2006. Most of the time these applications of Specman are setup to drive the hardware, but often for the purpose of verifying the entire system...(read more)

Emulation Is Here To Stay

2009-11-03T00:29:00Z

A recent blog by Brian Bailey covered the emulation war. I would like to correct some of the facts Brian has mentioned and also add my own comments. First, Brian, you owe Cadence an apology :) You forgot some of the emulation announcements from Cadence. You mentioned Nethra Imaging, AMD and Silicon Hive as the ones that were announced in the past year. You forgot the following announcements: Sharp , Netronome , ICT and the recent nVidia announcement about their Palladium usage at the Fermi project...(read more)

From Cadence Earning Call This Week

2009-11-02T19:01:00Z

In system development, we have focused on two key customer challenges. First, we are increasing their productivity by elevating design and verification to the next level of abstraction. This quarter, we announced the industry’s first transaction-level modeling, or TLM, design and verification flow. We also announced integration of this flow to support leading embedded software environments, enabling OVM -based, hardware / software co-verification. Second, we introduced a system validation solution...(read more)

Improve Productivity Through Communication and Learning

2009-11-02T15:00:00Z

I regularly spend time talking to people about the importance of the connection between embedded software and hardware design and verification. If you have been following my writing on cadence.com you know that it takes more than tools to succeed on a project that depends on hardware and software working together. I have written about embedded software verification and how to improve it. I have also written about companies that have reorganized people to report to common management that is responsible...(read more)

4G Is Here Now

2009-10-27T13:00:00Z

If you have not heard about 4G yet, it is here now. Verizon has already paid earlier this year $9.4B for an open access to the new spectrum. It'll be using the spectrum as the core of their high-speed 4G LTE network - see below. http://gizmodo.com/376103/verizons-936-billion-700mhz-plans-high+speed-4g-lte-network-up-and-running-before-att I predict, you will see many new designs (mobile, Wimax and base stations) addressing the new 4G standard. Every time, this is happening, companies need to...(read more)

Keeping Trident Missiles "On Target" With System-Level Verification

2009-10-23T22:00:00Z

Can you think of a more critical application for system-level verification than making ABSOLUTELY CERTAIN a missile carrying nearly 5 Megatons of nuclear payload doesn't have any "bugs"? We've all seen enough James Bond and Superman movies to understand what can happen with "wayward" missiles! So I wanted to point out a very good article appearing in this month's issue of Evaluation Engineering. It describes how a team of engineers at Draper Labs used a verification...(read more)

Synopsys’ “Synphony” Announcement – Welcome to the Party!

2009-10-14T21:39:00Z

I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge productivity boost that'll come from working at a higher level of abstraction, perhaps the semiconductor industry could enter a new golden-age. Until this year, customers have been intrigued with high-level synthesis, but cautious about whether it’s...(read more)

Webcast: EDA, ESL and More Ideas From DAC

2009-10-13T14:41:00Z

From the events calendar, OpenSystems Media is hosting a webcast tomorrow titled EDA, ESL, and More Ideas from DAC that will be hosted by Don Dingee and feature presentations and discussion from Frank Schirrmeister from Synopsys, Shabtay Matalon from Mentor, and myself. The event is Wednesday October 14 at 11:00 AM PDT and registration is open. Also this week there are two ISX presentations at CDNLive! San Jose that can be viewed from the comfort of your desk. Both are on Friday October 16. The first...(read more)

Virtualization and Simulation Roundtable

2009-10-13T14:03:00Z

A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com . Please have a look if you are interested in Virtual Platform usage for embedded software. One of the things that became clear right away is there are way too many terms which mean different things to different people. Peggy meant well by trying to stir up controversy by asking the difference between simulation and virtualization, but the question caused nothing...(read more)

Intrusive Software Debugging: Friend or Foe?

2009-10-06T13:00:00Z

One of the great benefits of working with simulation (RTL, SystemC , or any Virtual Platform) is the ability to provide non-intrusive interactive software debugging. Interactive software debugging provides the control and data access needed to inspect the state of the hardware and software in a running system. Because everything is simulated, it is easy to read and write memory without any actual simulation. This is in contrast to working with hardware. With hardware there is usually no way to peek...(read more)

Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

2009-10-04T00:39:00Z

Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009 . With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attendance than back in 2007 (our biggest ever). Those of you attending last year might remember that at that time Cadence had just announced our next-generation high-level synthesis tool, and that we were “back in the game” of System Design and Verification...(read more)

Must Have Advanced Verification to Achieve Software Signoff

2009-09-24T13:00:00Z

In a recent blog on EDA Graffiti , Paul McClellan he talks about Software Signoff. He loosely defines it as high level synthesis of C/C++ describing the system, with some of the code built into an FPGA and the rest remains application software. He identifies the two enabling technologies as 1) high level synthesis and the 2) FPGA. Those are necessary but not sufficient for Software Signoff. What's missing is functional verification. There's a big assumption made, that the software and FPGA...(read more)

What's the New CMO Mean For Cadence and System Design and Verification?

2009-09-22T16:10:00Z

If you track Cadence stock or other EDA leadership news you undoubtedly know we've hired John Bruggeman as our new Chief Marketing Officer (CMO) and Vice President of Marketing. He's been part of some very dynamic companies, and most recently with Wind River, whose sale to Intel led to eventual arrival at Cadence. Given his recent experience with embedded software at Wind River, one might surmise that Cadence will "do something spectacular" in embedded software. John popped out...(read more)