Back in November, our Japan office hosted a C-to-Silicon
Compiler user meeting. They host about two per year, and the meetings have been growing
in size and content. The November session drew 44 customers, representing 13 companies.
The content spanned about a half day, covering a wide variety of topics.
The user meeting started off with a C-to-Silicon business update,
presented by our Japan region marketing lead for system design and
verification, Makoto Yoshida. This included a high-level view of adoption
trends for C-to-Silicon, so customers can see what types of designs besides
their own are now being done with C-to-Silicon Compiler. I covered some of this
information in a previous blog
Yuji Watarai of Fujitsu VLSI's High Speed & Imaging
Product Business Unit then did a presentation entitled "Can C-to-Silicon
Compiler replace conventional design methodology?," specifically focusing on the
quality of results when pipelining a design with C-to-Silicon versus manually
coding it in RTL and retiming in RTL synthesis. Because high-level synthesis
does not require manual coding of the micro-architecture, it gives the designer
more freedom to explore different options, which is what Watarai-san and team did.
The final results they achieved were comparable to RTL but they were able to
achieve these results much more quickly with C-to-Silicon Compiler.
Then Ryoji Hashimoto of Renesas Electronics Corporation
presented details of their adoption of C-to-Silicon for their HEVC/H.265 IP (Cadence
announcement here, Renesas announcement here).
Hashimoto-san described the methodology that they implemented, highlighting the
reduced need for RTL verification, as the focus of functional verification
could be moved up in abstraction. He also outlined the engineering change order
(ECO) flow that they implemented in case they had to make a late-stage change
to the design. Hashimoto-san also presented some interesting productivity
ratios that they measure - they were able to achieve 3.22X more k-gates per
man-month with this new methodology, and simulation speed was 6X faster than
the previous version of this IP. These are impressive numbers, especially
considering how complex and high performance this IP is.
One area that Renesas wants to address in future projects was
covered in Casio's presentation, "A new circuit structure exploration
methodology by using C-to-Silicon Compiler and RC Physical". Casio's Masateru
Nishimoto presented the results of their detailed exploration of what
information can be fed back from RC-Physical to C-to-Silicon, and how
C-to-Silicon can use it to reduce wire congestion. Because C-to-Silicon
operates at such a high level, its optimizations can have dramatic effects one
way or another on physical routing congestion. Nishimoto-san illustrated the
effects of various techniques using a face detection design, and presented some
very good methodology suggestions for how to feed back guidance from
RC-Physical so that C-to-Silicon can properly optimize logic in those areas in
the physical floorplan that are prone to congestion.
Then Cadence's own Yoshi Watanabe presented the results of
some great work that he, Michele Petraca, and our Japanese AE team are doing in
connecting the hardware and software worlds, in a presentation and demo
entitled "Is it possible to develop and debug software using high-level
synthesizable description for C-to-Silicon Compiler?" This presentation was
very well received by the customers who were responsible for driver
The presentations wrapped up with an overview of
new C-to-Silicon features launced in 2013, presented by one of our talented Japanese
AEs, Yoichi Dohki. If you're looking for more information on that topic in
English, check out this
recent blog post.
Our Japan team works hard, but they also know how to
properly cap off one of these meetings with a beer reception. This provided the
opportunity for the attendees to talk in more detail with the presenters, and gave the Cadence folks some good insight on what they would like to
see in terms of future development direction. Thanks to our Japan team for
another great user meeting!
These types of meetings supplement Cadence's
broader regional CDNLive events, allowing more detailed focus on a
particular topic. We have also run them in other regions and even in companies
where we have a critical mass of users looking to share knowledge. Hopefully
this is something that grows over time!