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Developing the Skill Set Required for SystemC TLM-Based Hardware Design and Verification

Comments(1)Filed under: High-Level Synthesis, ESL, C-to-Silicon, SystemC, RTL, TLM, hls, RTL Compiler, metric-driven verification, System Design and Verification , C++, C, verification turnaround, time-to-market, IEDEC, transaction-level modeling, university software program, Cadence Academic Network

I've written a lot about the benefits of moving hardware design and verification up in abstraction from RTL to SystemC with transaction-level models (TLM). We have seen many customers speed their overall design and verification turnaround by 2x. A recent article described Fujitsu Semiconductor's experience -- 35% better performance, 35% smaller area, 51% less power and faster turnaround time.

The benefits of moving up in abstraction are summarized by the following graph, which shows the leaps in productivity for every leap in abstraction:

The obvious question is, if this is so great then why hasn't everybody already made the switch? Some of the reasons are historical and have already been addressed.

  • The early high-level synthesis (HLS) tools only supported datapath logic; control logic would still have to be described in RTL. So functional verification still had to focus on RTL, where the datapath and control were finally put together. Given that functional verification is the critical path in most projects, this blunted one of the main benefits.
  • Another factor was the use of non-standard inputs to HLS, preventing full production methodologies (including verification!) from being built around the high-level model. Fortunately, modern HLS tools support datapath and control together in a standard language.
  • Finally, the older HLS tools could not match the quality of results (QoR) of handwritten RTL, making their adoption a non-starter. Cadence's C-to-Silicon Compiler, which embeds RTL Compiler synthesis to guide its optimization, addresses this quite nicely and thus is seeing widespread production adoption.
  • Building the methodology and ramping up on tool usage, of course, are challenges that groups have to overcome. But this is straightforward and design teams constantly adopt new tools and methodologies, and EDA vendors like Cadence partner with them to assist.

So what is slowing the adoption of SystemC/TLM-driven design and verification? It's the skill set required.

At Cadence, we have worked with hundreds of engineers to adopt C-to-Silicon HLS and TLM-driven verification. Many of those were switching from other HLS tools, so they had already acquired the skill set. But among the groups migrating from RTL, it is rare to find an engineer that already possesses the entire required skill set, which consists of:

  • Hardware architecture design
  • Hardware micro-architecture for meeting QoR goals
  • C++
  • SystemC
  • High-level synthesis (HLS) tool operation
  • Understanding of RTL synthesis concepts, especially performance, power, and area analysis and optimization

We have seen software engineers pick up SystemC pretty easily, since it's just a class library built on C++. However, they have struggled to develop SystemC that synthesizes to competitive hardware. A great example was cited in ITRI's article where they tried to synthesize a C++ software implementation of an ECC block. Once they applied their hardware expertise to re-architect the code to more efficiently target hardware, they reduced the area of the ECC by 17x!

Hardware design, architecture, micro-architecture, and understanding how to apply the above to optimize performance, power, and area, is a set of skills unique to those with hardware design training and experience. However, hardware designers typically have not used C/C++ very much since their university days. Typically a hardware engineer can become proficient with C++ and object-oriented concepts in a matter of a couple months, and SystemC is only a couple more weeks to learn after that.

Back in the 1990's, thousands of engineers went through a similar retooling where they learned Verilog, RTL, and synthesis as they moved up from gate-level schematic design. However ,in today's economy, we are seeing a lot of companies operating with such a lean engineering staff that they cannot get enough down time to re-tool. Which is too bad when you consider the return on such an investment.

That leaves us to look to universities -- they are preparing the next generation of hardware designers, so they should be preparing them with the required skill set. And we are already seeing courses developing this skill set. Early leaders include Professor Luciano Lavagno's Modeling and Optimization of Embedded Systems at the Polytechnic University of Turin in Italy, Professor Luca Carloni's CSEE 6868E System-on-Chip Platforms at Columbia University, and most recently Professor Hiroshi Saito's SYA08 Electronic Design Automation for System-Level Design at University of Aizu in Japan. In fact Cadence has already seen students of Professors Lavagno and Carloni get hired into our customers to help drive adoption of these new techniques.

Cadence's University Software Program has been instrumental in helping facilitate the development of such curricula, starting with the collaboration between Cadence and these bellwether universities. Much of the coursework utilizes TLM-Driven Design and Verification Methodology, a comprehensive text written by several Cadence architects in collaboration with Brian Bailey. The University Software Program has since facilitated collaboration between these universities and others who wish to develop courses in this area. And it offers the Cadence Academic Network on LinkedIn to facilitate online peer-to-peer support, discussions, and information. I recently presented this information to other universities at the Interdisciplinary Engineering Design Education Conference (IEDEC); the paper is archived at the IEEE site and my slides are available on SlideShare.

So there are plenty of resources available to help develop engineers with this skill set, whether you are in the commercial sector or the academic world. The academic world is working to increase the supply of talent, but for companies looking to gain a time-to-market and efficiency advantage now, it would be wise to make the investment now. The most important thing to focus on is the ROI of adopting higher-abstraction design and verification. The last leap from schematics to RTL drove the industry for the past 20 years. It's time we start investing so that the next 20 years can be just as prosperous for the electronics industry.

-Jack Erickson

Comments(1)

By Srinivasan Venkataramanan on June 19, 2013
Interesting article. Is this course work from CDN available for institutes such as ours (www.cvcblr.com) to train students/working professionals? We've been in this business for last 9 years and have been a good partner with CDN's Verification Alliances. Would be interested in exploring HLS for near future. Thanks Srini

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