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DAC 2013 – System Design on Wednesday, June 5th

Comments(0)Filed under: Emulation, ARM, Palladium, nVidia, Broadcom, RPP, Bluespec, Freescale, Schirrmeister, AMD, Dini, FPGA Based Prototyping, Texas Instruments, virtual prototyping, Software Debug, DAC2013, Hybrid Prototypes, ARM Fast Models, sTec

The DAC exhibition comes to a close today, and we have another day with great presentations related to the Cadence System Development Suite. If you want to follow along the flow of our core engines from virtual through RTL simulation, acceleration, emulation and FPGA-based prototyping, we just created a new video landing page outlining the successes of Xilinx, Nvidia, Broadcom, Freescale and partner comments from ARM and Bluespec. Yours truly is giving a brief overview of how it all fits together on this page as well.

Yesterday's panel on the future on "Hardware-Assisted Development in 10 Years: More Need, More Speed" was a great event. In the photo above you see Paul McLellan (SemiWiKi), David Bural (TI), Alex Starr (AMD) and Mehran Ramezani (Broadcom). The panelists considered emulation capacity and its current roadmap as OK, but commented that they could use more speed. They see hybrids with virtual prototypes for a speed-up as well as hybrid use of FPGAs for stable sub-systems emerging. There was lots of discussion on how FPGA-based prototyping systems could fill the speed gap to get software developers into the 10MHz range, as well as the specific differences on which engines can be best used when in the design process and what their specific advantages and disadvantages are. Enough for a follow-up Blog J

One presentation I missed in yesterday's preview write-up was a joint Freescale / Cadence presentation on using Palladium XP for DMA/PCIE performance validation and analysis. Focus was on sub-block-level analysis along with complete system-level verification using emulation. Key factors for using Palladium at Freescale for this purpose were speed, debug visibility of internal signals and fast turnaround of system builds.

Today is a system design hardware day augmented with some connected virtualization - just like the panel yesterday was outlining. At 11:30 our partner BlueSpec will kick off the theatre presentations by describing "The Best of Both Worlds - Combining Virtual and FPGA-based Prototypes." This presentation goes along with a video compression demo we give at the booth. The results speak for themselves - the hybrid combination of VSP Virtual Prototyping and RPP FPGA-Based Prototyping executes software faster and improves HW/SW debug, addressing key software development challenges for complex chips.

At 1 pm Lecroy will present on "Ubiquitous PCI Express Verification from Simulation through Post-Silicon Development." The key here will be all about debug using their SimPass offering. They will show how users connect their RTL design in Palladium to the SpeedBridge® adapter, connect the SpeedBridge to the target system like a motherboard, live ethernet traffic, video camera, etc., generate SimPASS trace files as the user RTL runs in Palladium and then load the trace files in SimPASS for graphical debug and analysis. Connecting emulation to the real system environment is crucial and this combination allows efficient debug.

At 1:30 pm Freescale will present on "Leveraging Fast Models with Palladium XP for performance validation to scale with SoC growth." This will again be about hybrids with virtual models - this time the connection is established between emulation and ARM Fast Models as they can be integrated into VSP. The challenges Freescale is addressing with this approach are multiple projects using Palladium as a high-demand resource, the growth of future chip capacity requirements beyond current available resources, the complex workloads that demand greater performance as well as the strong requirement to enable more software development.

At 3:30 pm, DINI will present on "Hardware Solutions for FPGA-based Prototyping," outlining the specific needs on the pure hardware side combined with the need for an efficient bring-up flow - in this case compatible with the flow our Palladium emulator already uses. The combination of emulation and FPGA-based prototyping becomes quite efficient and attractive as it allows users to balance speed and capacity with debug and bring-up requirements.

The final presentation of the day and for System Design in the Cadence DAC Theatre will be given by sTec at 5 pm. The presentation will summarize the characteristics and primary use models for the ASIC verification platforms that sTec uses: gate-Level simulation, RTL simulation, Palladium emulation and RPP FPGA-based prototyping. The main use cases then described will be pre-silicon verification and software (firmware) development.

What a DAC this was for System Design - we had 14 customer and partner presentations at our booth! It will be interesting to see the progress between now and we meet again at DAC2014 in San Francisco! 



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