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DAC 2013 – System Design on Tuesday, June 4

Comments(0)Filed under: Emulation, IBM, Palladium, software, RPP, Freescale, Schirrmeister, AMD, FPGA Based Prototyping, virtual prototyping, System to Silicon Verification, DAC2013, Coverage

We had a great day on system design yesterday, followed by great party at Austin City Limits with "Asleep At The Wheel" and the EDA band around Jim Hogan. Today shapes up to be just as great!

We started early today at 8:00am with our Cadence System-to-Silicon Breakfast. Brian Fuller was moderating, Mike Stellfox introduced the challenges of today's designs followed by AMD's Alex Starr talking about their use of emulation and how it is augmented with virtualized environments.  Mihir Pandya from Freescale continued with an overview of bringup of a sub-system in FPGA-based prototyping, and Avi Ziv from IBM talked about coverage and 24x7 verification challenges. There was an interesting panel afterwards, which Richard Goering or I will cover in a future blog post.


Later in the day we again have a great line-up of presentations at the Cadence DAC Theatre, as well as a hig- profile panel on the future of hardware-assisted verification in the DAC Pavillion.

Starting at 11:30am, Forte and Cadence will present together on "How to Broadly Deploy SystemC High-level Synthesis for Production Hardware Design". While we are obviously competing on winning customers day to day, this will be an interesting market overview about the general challenges and reasons to move up to high-level synthesis, as well as the overall market dynamics high-level synthesis introduces, including new approaches to verification.

Our own Raghu Binnamangalam will present on Palladium's low-power optimization capabilties in, "Smarter, Greener Systems with Superior Productivity and Increased Predictability Using Dynamic Power Analysis" at the DAC Designer Track, Hall 5, Session 3.20. Low power is becoming more and more crucial for our customers. Cadence Palladium has quite a lead with our patented "Dynamic Power Analysis", recently described by TI and Broadcom. Users get more than 90% chip-accurate estimates well before silicon and make it a requirement for tape-out.

Marvell will talk at 12:30pm about "SoC Interconnect Analysis for Effective Verification, Architectural Exploration and Post-silicon Debug", using our Interconnect Workbench. This is all about the classic performance analysis, often done prior to RTL. But these days, the interconnect has become so complex that a lot of it is best done actually using the real automatically generated RTL. Marvell will talk about some of the key results they have achieved in different scenarios, including a video engine cross-bar, for which the write performance inhibited pipelining requests as quickly as possible, which was root caused back to a write performance drop due to incorrect IP configuration. Other scenarios include traffic stress from multiple DMA engines and PCI Express performance.

At 1:00pm, Texas instruments will present "Validation Methods of SoC Bus Fabric Performance Using Synthesizable SerDes BFMs on Palladium". The challenges TI is trying to address include optimization of Palladium throughput for large datasets in its SoCs with SerDes-based peripherals, stress testing and characterization of SoC fabric performance, as well as pre-silicon software development. The results TI will show include validation software re-use from pre-silicon to post-silicon, ready by first silicon, delivery of software drivers with silicon, verification of data sheet performance specs, as well as development of the IDE during the pre-silicon stage.

At 2:00pm, Methods2Business will describe a path "Towards Formally Proven Embedded System Design with an Unambiguous HW/SW Contract". We will hear about the concept of "contract-based embedded system design" using software design automation with formal verification based on Verum's toolset, virtual prototyping for earlier, better and more software validation, and formal verification to guarantee correct hardware and software. This presentation will show interesting use cases of virtual platforms using our VSP, extending to hardware verification.

Finally, at 4:00pm, we will have a DAC Pavillion Panel that I helped organize called "Hardware-Assisted Development in 10 Years: More Need, More Speed". SemiWiki's Paul McLellan will moderate a panel with AMD's Alex Starr, Texas Instrument's David Bural, and Broacom's Mehran Ramezani. The DAC program reads in Texas style that "Emulation has come a long way, y'all! Panelists explore who benefits, and the state-of-the-art in hardware-assisted development systems today and in 10 years. Share these users' visions on design and verification complexity and how they plan to overcome these challenges through next-generation technology including emulation, acceleration, and prototyping."

I certainly will come prepared with my questions and hope to see y'all there!


Frank Schirrmeister


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