You may or may not have noticed that Cadence's DAC Theater schedule features an intriguing combination of presenters next Tuesday:
Tuesday, June 04, 2013
|11:30 AM||Forte and Cadence||How to Broadly Deploy SystemC High-level Synthesis for Production Hardware Design|
The obvious question is, "Why are two high-level synthesis direct competitors presenting together?"
The answer starts back at an "experts at the table" panel session on high-level IP that occurred back in February. Brett Cline from Forte and Mark Warren from Cadence were among the participants, and found themselves agreeing on every point. It made for a less-than-exciting panel discussion, but as companies, we realized that we both share the same mission - to help companies more efficiently design and verify competitive IP by moving to SystemC-driven high-level synthesis.
So in this theater presentation, Mark will share the stage with Mike Meredith from Forte. Both lead the technical field deployment efforts for their respective companies, and they will share their experiences in helping companies and engineers move up from RTL to high-level design and verification with SystemC. The presentation will briefly outline "the why" (the benefits of making this move) and then will focus mostly on "the how". How you go about acquiring the skills, how you incorporate it into your methodology, how you choose the right projects, etc.
It should make for not only an interesting presentation, seeing competitors co-present, but it will be a great opportunity to learn how to increase your company's competitiveness in developing new IP. I'll be covering this session on Cadence's new live blogging platform, which you can find on the Cadence DAC website's multimedia tab. Look for my insights and observations. And, for those attending DAC, I hope to see you there!