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DAC 2013 – Software Driven EDA for the “Age of Gods”

Comments(0)Filed under: Acceleration, Emulation, ESL, DAC, virtual platforms, System-Level Design, System Development Suite, rapid prototyping, FPGA-based prototyping, Design Automation Conference, virtual prototyping, software-driven EDA, hybrid engines, DAC 2013, RTL simulation, Cadence theater

This year's Design Automation Conference is less than a week away, and it's time for my preview of what to see at DAC. Last year I had likened my passion for system-level design to the Energizer Bunny, keeping on drumming. Maybe that year was the DAC of system-level design. The trend continues. We have even more customers and partners presenting at the Cadence DAC Theatre on system-level design and verification, but as I wrote last week in my Blog in Chip Design Magazine, from here on out we are really looking at a new time in the front end of EDA. Alberto Sangiovanni-Vincentelli had predicted the key role of software in his keynote at the 40th DAC ten years ago, likening the age we are in again to the "Age of Gods" as described by Giovan Battista Vico. Former Montavista founder and Linux guru Jim Ready recently started calling it "Software Driven EDA".

All the system-level design drivers I had outlined last year - technology consolidation continuing, design chain enablement becoming a key requirement, standards enabling interoperability, links to verification finding adoption and foundries embracing system-level - are still key elements driving the direction of EDA. Software sticks out though as main requirement, both enabling software development at all layers of the software stack as well as using software itself for verification.

Besides enabling software -- literally all partners and customers in the list of my recommended DAC activities talk about software -- the main trend that becomes clear when looking at the customers and partners presenting. It is the connection of the different verification engines - virtual prototyping, RTL simulation, acceleration & emulation and FPGA based prototyping.

Sunday, June 2nd Software Perf. Analysis Virtual Proto RTL Simulation Emulation FPGA Based
5:00pm “The Myth of the $170 Million Dollar Design”, DAC Welcome reception with Gary Smith discussion of market trends, Austin Convention Center, Ballroom ABC Lobby This year's talk will focus on multi-platform designs and virtual prototypes which will cause an explosion in new design starts along with the annual EDA forecast. V V V V V V
Monday, June 3rd Software Perf. Analysis Virtual Proto RTL Simulation Emulation FPGA Based
9:30am Implementation of a Multi-threaded 64-bit Power Architecture Core on the RPP, FPGA-based Prototyping System V V V V
Freescale, Mike Schinzler
Cadence DAC Theatre
12:30pm Complementing In-Circuit Emulation with Virtualization for Improved Efficiency, Debug Productivity and Performance V V V V V
AMD, Alex Starr
Cadence DAC Theatre
2:00pm Accelerating Time to Market with ARM Software Development Tools and the Cadence System Development Suite V V V V V
ARM, Ronan Synnott
Cadence DAC Theatre
2:30pm Faster System Bring-up with an Embedded Testbench on Palladium V V V
Broadcom, Mehran Ramezani
Cadence DAC Theatre
Tuesday, June 4th Software Perf. Analysis Virtual Proto RTL Simulation Emulation FPGA Based
8:00am Doors Open 7:30am Breakfast Discussion moderated by Brian Fuller: The Cadence System-to-Silicon Verification Breakfast V V V V V V
Austin Convention Center, Level 4, Ballrooms E and F You can register here
Mihir Pandya, Freescale Avi Ziv, IBM Alex Starr, AMD Mike Stellfox, Cadence
Join us for a free breakfast to learn how next-generation system and SoC verification offerings from Cadence accelerate your system integration and reduce time to market. Learn about the newest capabilities of the Cadence System Development Suite, including Virtual System Platform virtual prototyping, Incisive® advanced verification, Palladium® acceleration and emulation, Rapid Prototyping Platform FPGA-based prototyping, and the Verification IP catalog, which adds new communication protocols and now supports acceleration and emulation. Listen to discussion about the latest methodologies for advanced verification and example applications from key Cadence customers. Be sure to bring your toughest questions for our expert’s panel.
11:30am How to Broadly Deploy SystemC High-level Synthesis for Production Hardware Design V V V
Forte & Cadence
Cadence DAC Theatre
12:00pm to 1:30pm Smarter, Greener Systems with Superior Productivity and Increased Predictability Using Dynamic Power Analysis V V
Raghu Binnamangalam, Cadence
Designer Track, Hall 5, Session 3.20
12:30am SoC Interconnect Analysis for Effective Verification, Architectural Exploration and Post-silicon Debug V V
Marvell
Cadence DAC Theatre
1:00pm Validation Methods of SoC Bus Fabric Performance Using Synthesizable SerDes BFMs on Palladium V V V
Texas Instruments
Cadence DAC Theatre
2:00pm Towards Formally Proven Embedded System Design with an Unambiguous HW/SW Contract V V V
Methods2Business, Marleen Boonen
Cadence DAC Theatre
3:00pm Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis V V V V
Freescale & Cadence
Cadence DAC Theatre
4:00pm to 4:45pm Hardware-Assisted Development in 10 Years: More Need, More Speed V V V V V V
Moderator: Paul McLellan / SemiWiki, Los Gatos, CA Panelists: Alex Starr / Advanced Micro Devices, Inc., Boston, MA Vahid Ordoubadian / Broadcom Corp., Irvine, CA David Bural / Texas Instruments, Inc., Dallas, TX
Booth 509
Wednesday, June 5th Software Perf. Analysis Virtual Proto RTL Simulation Emulation FPGA Based
11:30am The Best of Both Worlds – Combining Virtual and FPGA-based Prototypes V V V V
Bluespec
Cadence DAC Theatre
1:00pm Ubiquitous PCI Express Verification from Simulation through Post-Silicon Development V V
LeCroy
Cadence DAC Theatre
1:30pm Leveraging Fast Models with Palladium XP for performance validation to scale with SoC growth V V V V
Freescale, Hillel Miller
Cadence DAC Theatre
3:30pm Hardware Solutions for FPGA-based Prototyping V V
Dini Group, Mike Dini
Cadence DAC Theatre
5:00pm Firmware Development and Pre-silicon Verification with FPGA-based Prototyping V V V V
sTec, Inc.
Cadence DAC Theatre
Thursday, June 6th Software Perf. Analysis Virtual Proto RTL Simulation Emulation FPGA Based
1:30pm to 3:00pm Using Virtual Platforms for Firmware Verification V V V
Designer Track, Virtual Platforms and Prototyping, 18c
Jason Andrews

As previously outlined, none of the engines fits all needs users have. Each one of them has specific sweet spots in the design flow, combined with supporting use models.

Virtual Prototyping is primarily used for early software development and verification of driver software as well as bring up of operating systems and middleware. Its other supporting use models are:

  • Hybrid connections with RTL simulation, allowing software driver development and verification with a better balance of speed and accuracy
  • Hybrid connections to emulation and FPGA based prototyping, to enable software driven verification by booting through operating systems faster
  • Advancing the development of post-silicon verification by starting the development of scenarios on TLM models well before RTL is available

RTL Simulation is used primarily for hardware verification of IP blocks. It allows advanced verification using specialized test benches including SystemVerilog, Specman e, etc. Other supporting use models are:

  • Hybrid connections with virtual models allowing software driver development and verification with a better balance of speed and accuracy
  • Acceleration - RTL simulation accelerated with HW assisted verification - allows for faster speed of the design under test (DUT) while maintaining the flexibility of advanced test benches

Emulation is used primarily for "In Circuit Emulation," verifying hardware - sub-systems and systems on chip - in its system environment, which includes connections to peripherals using rate adaptors, as well as the software running on processors in the system. This is by far the biggest portion of the HW assisted verification market. Other supporting use models are:

  • Acceleration - HW assisted verification of hardware combined with RTL simulation - allows for faster speed of the design under test (DUT) in emulation while maintaining the flexibility of advanced test benches in RTL simulation
  • Hybrid connections to virtual prototyping, better balancing speed (faster in virtual) and accuracy (peripherals and accelerators in RTL) to enable software driven verification by booting through operating systems faster
  • Hybrid connections to FPGA based prototyping, better balancing bring-up time and debug (much faster and better in emulation, allowing use with less mature RTL) and speed (better in FPGA after optimization). In this use case the already stable or re-used portions of the design are kept in FPGA.

FPGA based prototyping is primarily used for software development of lower level portions of the software stack and OS bring up, as well as hardware aware optimization of middleware, all in the context of real world peripherals. Other supporting use models are:

  • Hybrid connections to virtual prototyping, better balancing speed (faster in virtual) and accuracy (peripherals and accelerators in RTL) to enable software driven verification by booting through operating systems faster
  • Hybrid connections to emulation, better balancing bring-up time (much faster in emulation, allowing use with less mature RTL) and speed (better in FPGA after optimization). In this use case the already stable or re-used portions of the design are kept in FPGA.
  • Acceleration - HW assisted verification of hardware combined with RTL simulation - allows for faster speed of the design under test (DUT) in FPGA based prototyping while maintaining the flexibility of advanced test benches in RTL simulation

So this Design Automation Conference clearly is showing off Software Driven EDA, and it may well be the kickoff of hybrid engine combinations as well. See you next week! 

Frank Schirrmeister

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