Sometimes it is hard to explain why certain ideas take off and why others don’t. There are many stories of poor products that are more successful than much better products. There are also many stories about products that struggle in one time or place, but the same thing is a big hit at another time in history. This is especially difficult for engineers who tend to analyze everything.
Embedded World 2013 starts Tuesday (Feb. 26, 2013) in Nuremberg, Germany. Since the event revolves around embedded systems, you can be sure Cadence will be discussing a number of interesting embedded topics. One such topic is virtual platforms, where there will be a number of demos and a presentation with the general theme “virtual platforms are being connected to everything.” Below is the marketing picture.
More specifically, four key connection points will be highlighted:
1. Virtual Platform + RTL simulator
2. Virtual Platform + RTL + AMS simulator
3. Virtual Platform + Emulator
4. Virtual Platform + FPGA Prototype
Although the stand-alone SystemC virtual platform is a popular use model for software engineers, it has become clear that by itself it is not sufficient for many use cases. A stand-alone simulation that does not connect to anything else will always be limited compared to more connected solutions. Wednesday at 10 AM, there is a presentation and paper that I authored titled “Utilizing Mixed-Language Virtual Platforms for Programmable SoC FPGA Designs.” It covers methodology for mixing a virtual platform with RTL design blocks, and covers how to verify the system using a software-driven verification flow. This presentation is part of two sessions on Embedded System Design Automation.
There will also be demonstrations of the Cadence Virtual System Platform (VSP) connected to Cadence Palladium XP and the Cadence Rapid Prototyping Platform (RPP).
The picture below shows the connection between VSP and RPP over a PCI-Express link using SCE-MI.
It's been interesting for me to see which connection points make the most sense for a particular company, and how they can be different depending on company history and preference. Regardless, it seems everybody is facing a real challenge to develop a flow that goes from early software development and system verification to silicon that works for them.
It is also exciting for many of us at Cadence to see how users have been able to use a combination of virtual platforms plus emulation to get a higher performance solution for running complex operating systems such as Android and Windows RT, or how users have filled a missing virtual platform model using an FPGA platform, or how RTL IP development teams have been able to run real Linux device drivers with the full RTL of the hardware they are controlling and still boot Linux in a minute or two and start exercising the device driver.
I remember EDA companies trying to make all kinds of connections back in the late 1990's while trying to solve the same issues we are talking about today. I even found an old press release about Quickturn and Yokogawa Electric developing a hybird co-verification system. I'm sure some current Cadence people may have even worked on it. It's not that the ideas were bad, but they just didn't come at the right time or place in history. There could have been any number of technical reasons. Maybe the emulator wasn't a must have item for verification fifteen years ago, maybe the processor models were too slow, and most of all maybe the embedded multi-core software problem wasn't as big of a challenge as it is today.
When we set out to create the Cadence Virtual System Platform, we knew connected was a key Cadence strength, and Embedded World is great place to stop by and see the vision in action.Jason Andrews