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C-to-Silicon 12.2 Available for Your Holiday Shopping List

Comments(0)Filed under: C-to-Silicon Compiler, High-Level Synthesis, IP re-use, SystemC, hls, RTL Compiler, System Design and Verification, Jack Erickson, QoR, Flex Channels, C-to-Silicon 12.2, clock gating

The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a lot of it out because it has no benefit to me or does not solve a problem I have. Do I really need a $3000 zero-gravity massage chair? Maybe somebody does (actually, this is on my son's wish list, apparently he has stress as well as a problem with gravity). But all I see are a bunch of features that I'm not sure I really need -- my favorite being the color LCD display on the remote that shows the massage's progress. I guess the lesser models just show a spinning hourglass?

I do have a soft spot for those famous "As Seen on TV" product commercials, because they go to great lengths to create a problem that the product solves. Here is a highlight reel of these contrived problems.

Unfortunately, our industry faces real challenges. In the past year we have seen large semiconductor vendors re-focus from the highly-competitive mobile processor market to focus on longer-lifecycle products such as embedded devices for automotive, industrial, and "smart" home devices. We have seen systems companies in-sourcing chip design in order to create more differentiation in their products, even if they didn't already have in-house chip design expertise.

We have been working closely with some of these companies as they transform themselves. High-level synthesis is a key technology for speeding turnaround of short-lifecycle products -- it speeds design and verification for new IP, and makes re-targeting that IP for different applications and processes much easier. It can also help long-lifecycle products save on area (and part cost) by exploring a broader micro-architecture solution space. And HLS helps systems companies create differentiation - instead of having to hire an army of engineers to build and verify low-level RTL, they can focus on developing and verifying concepts and algorithms at the system level and automatically take them into RTL implementation and below.

And just in time for the holiday season, the latest version of C-to-Silicon Compiler is now available. The 12.2 release delivers:

Higher quality of results: C-to-Silicon already meets or beats the QoR of handwritten RTL because it has embedded RTL Compiler production synthesis to guide its high-level optimizations. The 12.2 release adds more precision for higher-frequency designs, along with some additional area optimizations. One beta customer saw a 7% area reduction with the new release (and they use that other RTL synthesis tool) and one very high-speed design saw an area reduction of 14% with better timing.

Ease-of-QoR: Ease-of-use can mean a lot of things ("easy storage!" "one size fits all!" "dishwasher-safe!" "push button!"), but it is meaningless if you can't achieve the QoR that you need to. So our efforts have focused on two areas -- automating the synthesis process as much as possible, and providing quick and useful feedback to help hardware designers make micro-architecture and implementation decisions.

A good example is the new synthesis mode capability in 12.2. It lets you specify based on the code in the SystemC process whether it's already cycle-accurate and should not have added states, whether you want to allow C-to-Silicon to freely add latency cycles so it can meet cycle time and reduce area, and whether to automatically break combinational loops. And the new multi-phase scheduler provides feasibility feedback much earlier in the run so you can focus on the basic issues before getting into more complicated situations and make adjustments much sooner.

Flex Channel enhancements: Flex Channels are direct point-to-point interface IP provided with C-to-Silicon. They contain transaction-level models (TLM) for channels and initiators to easily connect modules or blocks. Because they are at a high-level of abstraction, they simulate very fast and are easy to understand. But they have also been designed and tested to generate good quality of results.

New improvements in 12.2 enabled these models to utilize 100% standard SystemC constructs to describe all levels of abstraction with a single model, with no special wrappers or macros necessary. This means they not only get great QoR through C-to-Silicon, but they can be run in any other tool in your flow that supports SystemC.  These C-to-Silicon Flex Channels provide the building blocks to quickly create libraries of complex bus protocols.  Customers have been utilizing AXI bus libraries during the past year and getting excellent QoR.  Stay tuned for more details in that space...

Coarse-grained clock gating: Because high-level synthesis has a broad view of the control and data flow of a design, it enables higher-level optimizations. For instance C-to-Silicon has the ability to identify more opportunities for leaf-level clock gating than an RTL synthesis tool could, and it generates RTL that is structured so that the RTL synthesis tools can more easily insert clock gating logic (the actual logic still must be inserted in RTL synthesis because it is typically dependent on cell-level timing, area, power, and placement).

Coarse-grained clock gating is the ability to shut off the entire clock network for a given block, so it can yield big power savings. In the 12.2 release, C-to-Silicon can insert coarse-grained clock gating logic based on your input as to what block of logic should be shut off, what the enable condition is, and how you want to implement the gating logic -- for instance C-to-Silicon can instantiate a clock gating-integrated cell (CGIC) from your technology library. Inserting the gating logic at this level is important for micro-architecture exploration and verification purposes.

These are the major themes of the C-to-Silicon 12.2 release, which is available now (hopefully the zero gravity feature will be in the next release!). As always, there are more details on features available in the "What's New" section of the Release Notes in the C-to-Silicon manual. Happy Holidays!

Jack Erickson

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