Home > Community > Blogs > System Design and Verification > accelerated vip delivers value for firmware driver validation and integration
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

Comments(0)Filed under: System Design & Verification, Firmware, validation., Driver

Earlier this year, Cadence announced the expansion of its VIP Catalog to include Accelerated VIP (AVIP). AVIP is used together with Cadence's Verification Computing Platform to enable RTL verification.  AVIP running on the Palladium XP platform consistently executes hundreds of times faster than with simulation.   Obviously this is great news for validation teams since designs routinely exceed 50Mgates these days and much greater performance is needed. 

AVIP is also proving to be uniquely suited for another purpose: driver/firmware integration and validation.  Cadence is seeing strong demand from our customers for this need.   

One example I've been closely monitoring is Samsung Memory.  I thought I'd draw your attention to it since many of our customers could similarly benefit from this approach. 

Samsung has been using Cadence AVIP to verify their new PCI Express based solid-state drive (SSD) design.  Samsung SSDs are typically being employed in laptops and servers to reduce power and space and increase reliability relative to traditional hard disk drives.  

A bit of history...

This year Samsung Memory added a PCI Express interface to their SSD controller design.  The PCI Express design addition significantly increases transaction rates and reduce latencies relative to earlier SSSD generations.  To verify the block level protocol compliance of the new interface they began by using Cadence's simulation VIP.  This proved to be highly effective.  However, when the time came to do firmware/driver validation at the SoC level, they found the simulation environment wasn't sufficiently fast.  In fact, Samsung determined they'd need a validation environment capable of delivering hundreds of times greater performance. 

When they turned to Cadence for suggestions we recommended using our PCI Express Accelerated VIP (AVIP) with a C++ user interface designed for Palladium XP simulation-acceleration.  Since Samsung had already used our PCI Express simulation VIP, the transition to AVIP was even more straightforward than usual.  Within three weeks the accelerated environment was up and running.  This in itself was highly advantageous since it meant Samsung's driver developer/integrators would become productive much sooner than if they'd had to wait for an FPGA prototype.  It also enabled Samsung to realize validation productivity gains of 100%.  See the Samsung Memory success story for additional details. 

Summary

Samsung's experience, taken together with other customers has made clear that driver/firmware validation is becoming crucial step in SoC level validation.  In fact we are seeing rapidly increasing demand for this use model.   

Cadence AVIP optimizes Acceleration/Emulation to enable software driven use models.  Seeing this trend we are already working on ways to make firmware/driver validation even easier and faster.  If you've got a project nearing the SoC validation phase I'd urge you to connect with Cadence.  We're confident that AVIP in conjunction with our Palladium XP Verification Computing Platform and RTL simulation can help you to improve productivity and quality in your projects. 

Pete Heller

 

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.