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Being The Energizer Bunny at DAC … Championing System-Level Design and Verification ;)

Comments(0)Filed under: System Design and Verification, Emulation, Incisive, ARM, functional verification, DAC, Imperas, CDNLive, debug, System Development Suite, Palladium XP, Xilinx SDK, Design Automation Conference, in-circuit emulation, In-circuit acceleration, AMD, DAC breakfast, Methods2Business, LSI, Rohde&Schwarz, Dini, LeCroy, NextOp, celeration

As the EDA industry and its customers are preparing for the yearly show down at the Design Automation Conference (DAC), it is good to review what I said in the past. Well, two years ago I wrote a blog called "Maybe This Time" (inspired by the Sally Bowles song in Cabaret, I am a Musical Geek after all), in which I outlined the top five reasons why DAC 2012 will be the DAC of System-Level Design. Being in system-level design and verification is truly like being the Energizer Bunny. We are drumming on.

Let's see how my top five reasons from two years ago scale to 2012. They have intensified, for sure! And at the bottom of this post you will find a list of system-level events you should not miss at DAC 2012. See you next week!

My 2010 reason number five, "Technology consolidation has begun" is certainly still true. 2012 was the year in which CoWare, VaST and Synfora were acquired. Some disaggregation has happened since then, Mentor spun out high-level synthesis into Calypto, Intel acquired CoFluent. Cadence has officially fully entered the system-level market with the rollout of the System-Development Suite in May 2011. Just before this year's DAC, Ansys aqcuired Esterel Technologies in our adjacent market of embedded software. And Cadence rolled out the 2012 edition of the System Development Suite featuring new in-circuit acceleration and improvements to all underlying execution engines (virtual prototyping, RTL simulation, acceleration, emulation and FPGA based prototyping) individually. The market, with all major vendors playing in it, certainly shows signs of getting closer to maturity.

If you want to understand more about how the different technologies can interact to enable efficient system-level design, I specifically do recommend coming to our breakfast on HW/SW Co-Development on Tuesday morning. It will feature live presentations from AMD and LSI talking about their adoption of the System Development Suite, as well as video testimonials from Xilinx, NVidia and Freescale. For information and registration, click here.

My 2010 reason number four, "Design Chain enablement becomes a key requirement", has just become more and more important since 2010. Cadence is presenting at ARM's booth, they are presenting at ours, and the best testament for how a design chain interacts is the DAC panel discussing system-level models on Tuesday at 1:30, in which we have a system house (RIM), semiconductor providers (Qualcomm), IP vendors (ARM, Tensilica) and an EDA vender (Cadence) jointly discussing the question whether "one model fits all".

2010 Reason number three, "Standards enable interoperability," has continued to grow in importance. One item of note to me this DAC is the presentation by STMicroelectronics and Cadence about the next levels of standardization around SystemC TLM 2.0, Wednesday at 4:25pm at the North American SystemC User Group. To learn more about interoperability I recommend checking out presentations at the Cadence EDA360 Theater (booth 1930) given by partners (ARM, Dini, Imperas, LeCroy, Methods2Business, NextOp, Rohde&Schwarz) and customers (AMD, LSI, Xilinx on Acceleration/Emulation, Xilinx on Virtual Platforms). Standardization and Interoperability continue!

2010 Reason number two was "Links to Verification find adoption". Well, the System Development Suite itself combines engines executing more abstract transaction-level models (TLM) with engines at the traditional register transfer level (RTL) - simulation, acceleration/emulation and FPGA based prototyping. Other vendors in emulation as well as simulation are pushing similar links. All this is taking into account the software running on modern chips, and how it is used for verification as well as the engines enable its early development.

An event not to miss at DAC 2012 is the 10th ESL Symposium moderated by Wally Rhines, happening at 11:30 on Tuesday. I'll be on the panel myself together with Samsung, ARM, NEC and Mentor, and we will discuss "the role of software in addressing key system-level verification challenges, the requirements for introducing software at pre-silicon stages, and the need for multiple verification engines and design abstraction levels, such as virtual platforms and emulation, to balance maximum system verification cycles for the system, software or hardware validation objectives." We'll have fun! And you'll have a free lunch ...

I do expect my final reason in 2010 - that "Foundries are starting to incorporate system-level flows" - not to be as pronounced on the show floor as in previous years. However, the initial rollout and attention with foundry based ESL reference flows in the last two years has made a place for real adoption discussions. Several vendors have put on their DAC agenda "PPA characterization for TLM analysis and modeling," so they are trying to further connect high-level modeling with the actual underlying silicon technology. We even have these discussions with 3D-IC experts, for which system-level modeling becomes more and more important and whether a signal crosses between stacked chips or leaves a package can become the difference between failure and success of a project.

So are we there yet for system-level design and verification? Will this DAC be the DAC of system-level design? Well, having been involved in this domain for one and a half decades, I now can imagine how the ever drumming Energizer Bunny must feel. We are making progress. And are drumming on ...

And as promised, here are the system-level events not to miss for DAC:

Sunday, June 4th

6pm

DAC Welcome reception with Gary Smith discussion of market trends

Monday, June 4th

12pm

Exploring a double paradigm shift for embedded software development: virtual prototyping plus formally proven model driven software generation

Methods2Business, Marleen Boonen

Cadence EDA 360 Theatre

2:30pm

LTE-Advanced with Palladium XP

Rohde&Schwarz,  Andreas Roessler

Cadence EDA 360 Theatre

2:30pm

Panel: HW/SW Interface Management – The path to smoother HW/SW integration?

‘The Integration Forum’, Duolog Booth # 1520

Gary Stringham (Gary Stringham Associates), Frank Schirrmeister (Cadence)
Harry, the ASIC Guy, Kurt Shuler (Arteris)

4:30pm

Extensible Virtual Platform for the Xilinx Zynq-7000 EPP

Xilinx, David Beal

Cadence EDA 360 Theatre

Tuesday, June 5th

7:30am

Breakfast Discussion moderated by Steve Leibson, EDA 360 Insider: Addressing HW/SW Co-Development, System Integration, and Time to Market

270-276 (Moscone Convention Center)

08:00 “Hardware / Software Co-Development using the System Development Suite”
            Frank Schirrmeister, Cadence  featuring Xilinx, NVidia and Freescale
08:30 “Intelligent Instrumentation for AMD Fusion processors using the Cadence System Development Suite”, 
            Alex Starr – AMD
08:50" Combining Virtual Platforms, Emulation, and Hardware Prototypes”, 
            Chuck Cruse – LSI
09:10 “Accelerating HW/SW Validation using the Cadence Verification IP Catalog Featuring Accelerated Verification IP”, 
            Erik Panu, Cadence
09:30 “Q&A Panel Acceleration HW/SW Co-Development” – All presenters & Steve

10:30am

Cadence System to Silicon Solution for ARM big.LITTLE Designs

Cadence, Frank Schirrmeister

ARM Connected Community Pavilion at booth 802

11:00am

ARM Fast Models at the Heart of Virtual Prototyping

ARM, Robert Kaye

Cadence EDA 360 Theatre

12:00pm

Panel: 10th Annual ESL Symposium - Panel: The ESL Hotspot - Where Software and Hardware Meet

Gateway Ballroom, #104

The panel will discuss the role of software in addressing key system-level verification challenges, the requirements for introducing software at pre-silicon stages, and the need for multiple verification engines and design abstraction levels, such as Virtual platforms and emulation, to balance maximum system verification cycles for the system, software or hardware validation objectives.

Chair:              Wally Rhines, CEO, Mentor Graphics  Speakers:        
Nasr Ullah, Director of Performance Architecture, Samsung
John Goodenough, VP of Design Technology and Automation, ARM
Benjamin Carrion Schafer, Assistant Manager of NEC Central R&D Lab / Business
Development Manager for HLS Tools, NEC
Frank Schirrmeister, Sr. Director, Product Marketing, System Development Suite, Cadence Design Systems
Glenn Perry, General Manager of the Embedded Systems Division, Mentor Graphics

1:30pm

Panel: System Models - Does One Size Fit All?

Room 305

System-level modeling is a critical part of product design flows. Developing a single model that simultaneously satisfies the needs of software developers, system architects, hardware developers, and verification engineers is hard. Time of availability,usage models, accuracy requirements, development effort, and speed vary greatly. Is it possible for one size to fit all? Who will provide the models? Who will pay for them? The panelists will review different aspects of system modeling and discuss which abstraction levels best address specific user requirements.

Chair:              Brian Bailey - EETimes EDA Designline, Oregon City, OROrganizer:       Frank SchirrmeisterSpeakers:        
Stuart Swan - Cadence Design Systems, Inc., San Jose, CA
Rick Higgins - Qualcomm, Inc., San Diego, CA
John Goodenough - ARM, Inc., San Jose, CA           
Frederic Risacher - Research in Motion, Ltd., Waterloo, ON
Andrea Kroll - Tensilica, Inc., San Jose, CA

2:00pm

Zynq EPP – from RTL to success with emulation

Xilinx, Peter Ryser

Cadence EDA 360 Theatre

2:00pm

A deterministic flow combining Virtual Prototypes, emulation and FPGA-based prototypes

LSI, Chuck Cruse

Cadence EDA 360 Theatre

3:30pm

A new paradigm for system-level debug productivity

AMD, Alex Starr

Cadence EDA 360 Theatre

Wednesday, June 6th

09:00am

Panel: High-Level Synthesis Production Deployment: Are We Ready?

Room 105

High-level synthesis has historically over-promised and under-delivered, but that is all about to change. Or, is it? Are we ready to climb the ladder up to the next level of design abstraction? Watch our panelists debate whether today’s technology can handle system validation, IP integration and optimization, power/performance constraints, and design verification challenges. Find out if we are about to connect the world of embedded software development to hardware design.

Chair:              Clem Meas - quickSTART Consulting, Boulder, CO
Speakers:        
Eli Singerman - Intel Corp., Haifa, Israel
Mark Johnstone - Freescale Semiconductor, Inc., Austin, TX
Mark Warren - Cadence Design Systems, Inc., San Jose, CA
Vinod Kathail - Xilinx, Inc., San Jose, CA
Andres Takach - Calypto Design Systems, Inc., Wilsonville, OR

11:00am

Assertion Synthesis: A Power ‘App’ for Simulation, Formal, and Hardware-Assisted Verification

NextOp Software, Yuan Lu

Cadence EDA 360 Theatre

11:30am

Open Virtual Platforms (OVP) and Cadence VSP

Imperas, Larry Lapides

Cadence EDA 360 Theatre

3:30pm

Ubiquitous PCI Express verification from simulation thru post-Silicon development

LeCroy, John Weidermeier

Cadence EDA 360 Theatre

4:25pm

Beyond TLM 2.0: New Virtual Platform Standards Proposals from ST and Cadence

Stuart Swan, Cadence Design Systems, USA
Jerome Cornet, STMicroelectronics, USA

NASCUG, Moscone Center, San Francisco, CA

5:00pm

FPGA-based prototypes - to build or to buy?

Dini Group, Mike Dini

Cadence EDA 360 Theatre

Thursday, June 7th

1:30pm

Application of Virtual Platforms: SyMX -- Model Crossover between Simics and SystemC/TLM Virtual System Platforms
Location: 303
Christian Sauer - Cadence Design Systems, Inc

Frank Schirrmeister

 

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