Home > Community > Blogs > System Design and Verification > virtual divide and conquer to enable fixed sub systems
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the System Design and Verification blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Virtual Divide and Conquer Enables Fixed Sub-Systems

Comments(0)Filed under: verification, SystemC, TLM, FPGA, System Design and Verification, NASCUG, DVCon, virtual platforms, virtual prototypes, IP, Tensilica, Zynq, Xilinx, sub-systems, subsystems, fixed sub-systems, platform, OMAP

The 17th North American SystemC User Group meeting (NASCUG), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which I will report on some of the work we have done with Xilinx on their Zynq Extensible Processing Platform, which contains a fixed sub-system in both the actual silicon as well as the Extensible Virtual Platform associated with it.

So what is a fixed sub-system?

Sub-systems have been a standard practice in the ASIC and ASSP world for years. A good example is the OMAP platform from Texas Instruments. Somdipta Basu Roy reported on OMAP verification a while ago in a DVClub presentation. Slide 7 of that presentation talks about the verification approach, which not surprisingly makes heavy use of divide and conquer. A chip-level team integrates several sub-systems, all of which assembled from IP blocks themselves. The sub-systems themselves have already been verified locally by themselves. The verification task itself becomes quite daunting, as the reader is asked to "... now imagine that ~70 IPs, 10-15 subsystems per chip and 4-5 new chips are being done simultaneously (in parallel with 5 chips doing revisions) and 5 time zones."

Several of these sub-systems will contain processors and associated software, so they in fact look like mini-chips themselves; just 5-10 years ago they would have been considered to be very complex chips. Thus explains some of the need for sub-systems. They are just the next step of evolution in the world of IP reuse. Talking to market analysts, this reminds me of a presentation I watched a while ago at an IP-SoC conference in Grenoble. The basic tenor was that roles and responsibilities of IP vendors will be re-defined completely over the next couple of years.

There are three growth factors for the hardware design IP market:

  • Escalating cost of chip design: The design cost in advanced nodes continues to rise for hardware, a trend which is combined with escalating cost of embedded software design.
  • Increasing design complexity: Designs continue to migrate to advanced process nodes and innovation is moving from the chip-level to the system-level.
  • Shortening time window for new product introduction: The ever growing customer demand shortens product shelf-life and the actual product success rate is declining rapidly.

To address these trends, IP providers need to offer silicon-proven, pre-verified, pre-tested end-to-end IP solutions, addressing time to market constraints by offering larger fully-functional subsystems and by providing advanced design support services. A good example of that trend is provided by companies like Tensilica. They started by offering extensible processor cores. When users visit Tensilica's webpage now, they find a set of sub-systems specialized for HiFi Audio and Baseband Processing, combining hardware and software deliveries provided by Tensilica as an IP provider.

So what does that mean for virtual platforms?

The Zynq Extensible Processing Platform combines a programmable FPGA fabric with an ARM based fixed sub-system, multiple peripherals and interfaces to the FPGA fabric. Users can extend and customize the chip to their needs using the up to 3.5M gate equivalent FPGA. The actual delivery of the chip includes various operating system distributions, drivers for the core peripherals and development tools for programming.

One of those development tools is the Zynq Extensible Virtual Platform, which we co-developed with Xilinx. Just like its silicon counterpart, users get a fixed virtual sub-system, which they can extend with transaction-level models (TLM) to reflect the hardware blocks which eventually will end up in the FPGA fabric. I previously discussed the value of extending at the TLM level. It simply gets users to a vehicle to start software development much sooner, because development of the RTL takes significantly longer due to the increased detail it contains compared to TLM.

Bottom line, sub-systems are already a mainstream component for ASIC and ASSP development. IP providers are changing their roles to provide sub-systems combining hardware and software, and the development tools like virtual platforms are adding specific capabilities to enable sub-system delivery. The next step likely will be to automate more of the sub-system integration. Time will tell.

See you Monday at NASCUG!

Frank Schirrmeister

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.